Searched refs:VA1 (Results 1 – 3 of 3) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | use-sgpr-multiple-times.ll | 45 ; SI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]
50 ; VI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]
57 ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SA]], [[VA1]], [[VB]]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 659 static bool CC_RISCVAssign2XLen(unsigned XLen, CCState &State, CCValAssign VA1, in CC_RISCVAssign2XLen() argument
666 State.addLoc(CCValAssign::getReg(VA1.getValNo(), VA1.getValVT(), Reg, in CC_RISCVAssign2XLen()
667 VA1.getLocVT(), CCValAssign::Full)); in CC_RISCVAssign2XLen()
672 CCValAssign::getMem(VA1.getValNo(), VA1.getValVT(), in CC_RISCVAssign2XLen()
674 VA1.getLocVT(), CCValAssign::Full)); in CC_RISCVAssign2XLen()
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | use-sgpr-multiple-times.ll | 50 ; GCN: buffer_load_dword [[VA1:v[0-9]+]]
57 ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VA1]], [[SA]], [[VB]]
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