Searched refs:VPLL (Results 1 – 6 of 6) sorted by relevance
144 } else if (pllreg == VPLL) { in exynos_get_pll_clk()202 case VPLL: in exynos4_get_pll_clk()232 case VPLL: in exynos4x12_get_pll_clk()263 case VPLL: in exynos5_get_pll_clk()321 case VPLL: in exynos542x_get_pll_clk()443 sclk = exynos5_get_pll_clk(VPLL); in exynos5_get_periph_rate()656 sclk = get_pll_clk(VPLL); in exynos4_get_pwm_clk()717 sclk = get_pll_clk(VPLL); in exynos4_get_uart_clk()763 sclk = get_pll_clk(VPLL); in exynos4x12_get_uart_clk()799 sclk = get_pll_clk(VPLL); in exynos4_get_mmc_clk()[all …]
15 #define VPLL 4 macro
14 #define VPLL 4 macro
93 case VPLL: in s5pc110_get_pll_clk()
55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
333 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing