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Searched refs:VSEXT (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/X86/
DX86IntrinsicsInfo.h341 X86_INTRINSIC_DATA(avx512_cvtmask2b_128, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
342 X86_INTRINSIC_DATA(avx512_cvtmask2b_256, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
343 X86_INTRINSIC_DATA(avx512_cvtmask2b_512, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
344 X86_INTRINSIC_DATA(avx512_cvtmask2d_128, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
345 X86_INTRINSIC_DATA(avx512_cvtmask2d_256, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
346 X86_INTRINSIC_DATA(avx512_cvtmask2d_512, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
347 X86_INTRINSIC_DATA(avx512_cvtmask2q_128, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
348 X86_INTRINSIC_DATA(avx512_cvtmask2q_256, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
349 X86_INTRINSIC_DATA(avx512_cvtmask2q_512, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
350 X86_INTRINSIC_DATA(avx512_cvtmask2w_128, CONVERT_MASK_TO_VEC, X86ISD::VSEXT, 0),
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DX86ISelLowering.h288 VSEXT, enumerator
DX86InstrFragmentsSIMD.td125 def X86vsext : SDNode<"X86ISD::VSEXT",
DX86ISelLowering.cpp14145 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In)); in LowerTRUNCATE()
16023 return DAG.getNode(X86ISD::VSEXT, dl, VT, In); in LowerSIGN_EXTEND_AVX512()
16031 if (In.getOpcode() == X86ISD::VSEXT || In.getOpcode() == X86ISD::VZEXT) in LowerSIGN_EXTEND_AVX512()
16033 return DAG.getNode(X86ISD::VSEXT, dl, VT, In); in LowerSIGN_EXTEND_AVX512()
16080 return DAG.getNode(X86ISD::VSEXT, dl, VT, In); in LowerSIGN_EXTEND_VECTOR_INREG()
16132 return DAG.getNode(X86ISD::VSEXT, dl, VT, In); in LowerSIGN_EXTEND()
16161 OpLo = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpLo); in LowerSIGN_EXTEND()
16162 OpHi = DAG.getNode(X86ISD::VSEXT, dl, HalfVT, OpHi); in LowerSIGN_EXTEND()
16479 SDValue Sext = DAG.getNode(X86ISD::VSEXT, dl, RegVT, SlicedVec); in LowerExtendedLoad()
19339 ALo = DAG.getNode(X86ISD::VSEXT, dl, ExVT, A); in LowerMUL()
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dsext-in-reg.ll622 ; SI: v_mov_b32_e32 [[VSEXT:v[0-9]+]], [[SSEXT]]
623 ; SI: buffer_store_short [[VSEXT]]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86ISelLowering.h301 VSEXT, enumerator
DX86InstrFragmentsSIMD.td111 def X86vsext : SDNode<"X86ISD::VSEXT",
DX86ISelLowering.cpp5414 assert((X86ISD::VSEXT == Opc || X86ISD::VZEXT == Opc) && "Unexpected opcode"); in getExtendInVec()
5417 return X86ISD::VSEXT == Opc ? DAG.getSignExtendVectorInReg(In, DL, VT) in getExtendInVec()
17232 DAG.getNode(X86ISD::VSEXT, DL, MVT::v16i32, In)); in LowerTRUNCATE()
19276 X86ISD::VSEXT : X86ISD::VZEXT; in LowerEXTEND_VECTOR_INREG()
19341 return DAG.getNode(X86ISD::VSEXT, dl, VT, In); in LowerSIGN_EXTEND()
19585 SDValue Sext = getExtendInVec(X86ISD::VSEXT, dl, RegVT, SlicedVec, DAG); in LowerLoad()
25996 case X86ISD::VSEXT: return "X86ISD::VSEXT"; in getTargetNodeName()
29036 case X86ISD::VSEXT: { in ComputeNumSignBitsForTargetNode()
35891 SDValue NewVec = getExtendInVec(X86ISD::VSEXT, dl, VT, WideLd, DAG); in combineMaskedLoad()
39568 if ((InOpcode == X86ISD::VZEXT || InOpcode == X86ISD::VSEXT) && in combineExtractSubvector()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenFastISel.inc4622 // FastEmit functions for X86ISD::VSEXT.
5554 case X86ISD::VSEXT: return fastEmit_X86ISD_VSEXT_r(VT, RetVT, Op0, Op0IsKill);