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Searched refs:Z0 (Results 1 – 25 of 518) sorted by relevance

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/external/boringssl/src/crypto/fipsmodule/modes/asm/
D	aesni-gcm-x86_64.pl	`77 $Z0,$Z1,$Z2,$Z3,$Xi) = map("%xmm$_",(0..8)); 92 vpxor $Z0,$Z0,$Z0 # $Z0 = 0 100 vmovdqu $Z0,16+8(%rsp) # "$Z3" = 0 152 vpxor $Z0,$Xi,$Xi # modulo-scheduled 154 vpxor $Z1,$T1,$Z0 191 vpxor $T1,$Z0,$Z0 213 vpxor $T2,$Z0,$Z0 235 vpxor $Hkey,$Z0,$Z0 262 vpxor $T2,$Z0,$Z0 268 vpxor $Z1,$Z0,$Z0 [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/
D	if-pred-non-void.ll	21 ; CHECK: %[[SDEE:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.}}, i32 0 22 ; CHECK: br i1 %[[SDEE]], label %[[CSD:[a-zA-Z0-9.]+]], label %[[ESD:[a-zA-Z0-9.]+]] 24 ; CHECK: %[[SDA0:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.}}, i32 0 25 ; CHECK: %[[SDA1:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.}}, i32 0 26 ; CHECK: %[[SD0:[a-zA-Z0-9]+]] = sdiv i32 %[[SDA0]], %[[SDA1]] 27 ; CHECK: %[[SD1:[a-zA-Z0-9]+]] = insertelement <2 x i32> undef, i32 %[[SD0]], i32 0 30 ; CHECK: %[[SDR:[a-zA-Z0-9]+]] = phi <2 x i32> [ undef, %vector.body ], [ %[[SD1]], %[[CSD]] ] 31 ; CHECK: %[[SDEEH:[a-zA-Z0-9]+]] = extractelement <2 x i1> %{{.}}, i32 1 32 ; CHECK: br i1 %[[SDEEH]], label %[[CSDH:[a-zA-Z0-9.]+]], label %[[ESDH:[a-zA-Z0-9.]+]] 34 ; CHECK: %[[SDA0H:[a-zA-Z0-9]+]] = extractelement <2 x i32> %{{.*}}, i32 1 [all …]
D	if-pred-stores.ll	41 ; UNROLL: %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.}}, 0 42 ; UNROLL: %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.}}, 1 43 ; UNROLL: %[[v0:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND]] 44 ; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]] 45 ; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4 46 ; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4 47 ; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100 48 ; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100 49 ; UNROLL: br i1 %[[v4]], label %[[cond:[a-zA-Z0-9.]+]], label %[[else:[a-zA-Z0-9.]+]] 52 ; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20 [all …]
/external/llvm/test/Transforms/InstCombine/
D	select-cmp-cttz-ctlz.ll	9 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false) 20 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) 31 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false) 42 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false) 53 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) 64 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false) 75 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false) 86 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false) 97 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 false) 108 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false) [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
D	select-cmp-cttz-ctlz.ll	9 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false) 20 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) 31 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false) 42 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false) 53 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) 64 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false) 75 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false) 86 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %x, i1 false) 97 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %x, i1 false) 108 ; CHECK: [[VAR:%[a-zA-Z0-9]+]] = tail call i16 @llvm.cttz.i16(i16 %x, i1 false) [all …]
/external/clang/test/CodeGenObjCXX/
D	literals.mm	19 // CHECK: [[ARR:%[a-zA-Z0-9.]+]] = alloca i8* 20 // CHECK: [[OBJECTS:%[a-zA-Z0-9.]+]] = alloca [2 x i8] 25 …// CHECK: [[ELEMENT0:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8], [2 x i8] [[OBJECTS]], … 27 // CHECK-NEXT: [[OBJECT0:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1XcvP11objc_objectEv 28 // CHECK: [[RET0:%[a-zA-Z0-9.]+]] = call i8* @objc_retainAutoreleasedReturnValue(i8* [[OBJECT0]]) 32 …// CHECK: [[ELEMENT1:%[a-zA-Z0-9.]+]] = getelementptr inbounds [2 x i8], [2 x i8]* [[OBJECTS]], … 34 // CHECK: [[OBJECT1:%[a-zA-Z0-9.]+]] = invoke i8* @_ZNK1YcvP11objc_objectEv 35 // CHECK: [[RET1:%[a-zA-Z0-9.]+]] = call i8* @objc_retainAutoreleasedReturnValue(i8* [[OBJECT1]]) 71 // CHECK: [[ARR:%[a-zA-Z0-9.]+]] = alloca i8* 72 // CHECK: [[OBJECTS:%[a-zA-Z0-9.]+]] = alloca [2 x i8*] [all …]
/external/pdfium/third_party/lcms/src/
D	cmsintrp.c	452 X0, Y0, Z0, X1, Y1, Z1; in TrilinearInterpFloat() local 477 Z0 = p -> opta[0] * z0; in TrilinearInterpFloat() 478 Z1 = Z0 + (Input[2] >= 1.0 ? 0 : p->opta[0]); in TrilinearInterpFloat() 482 d000 = DENS(X0, Y0, Z0); in TrilinearInterpFloat() 484 d010 = DENS(X0, Y1, Z0); in TrilinearInterpFloat() 487 d100 = DENS(X1, Y0, Z0); in TrilinearInterpFloat() 489 d110 = DENS(X1, Y1, Z0); in TrilinearInterpFloat() 526 register int X0, X1, Y0, Y1, Z0, Z1; in TrilinearInterp16() local 554 Z0 = p -> opta[0] * z0; in TrilinearInterp16() 555 Z1 = Z0 + (Input[2] == 0xFFFFU ? 0 : p->opta[0]); in TrilinearInterp16() [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/StraightLineStrengthReduce/
D	slsr-add.ll	8 ; [[BASIS:%[a-zA-Z0-9]+]] = add i32 %b, %s 22 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s2 26 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], %s2 38 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %s, %b 42 ; CHECK: [[bump:%[a-zA-Z0-9]+]] = mul i32 %s, 3 43 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], [[bump]] 67 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s6 72 ; CHECK: [[bump:%[a-zA-Z0-9]+]] = shl i32 %s, 1 73 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = sub i32 [[t1]], [[bump]] 78 ; CHECK: [[t3:%[a-zA-Z0-9]+]] = sub i32 [[t2]], [[bump]] [all …]
/external/llvm/test/Transforms/StraightLineStrengthReduce/
D	slsr-add.ll	8 ; [[BASIS:%[a-zA-Z0-9]+]] = add i32 %b, %s 22 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s2 26 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], %s2 38 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %s, %b 42 ; CHECK: [[bump:%[a-zA-Z0-9]+]] = mul i32 %s, 3 43 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = add i32 [[t1]], [[bump]] 67 ; CHECK: [[t1:%[a-zA-Z0-9]+]] = add i32 %b, %s6 72 ; CHECK: [[bump:%[a-zA-Z0-9]+]] = shl i32 %s, 1 73 ; CHECK: [[t2:%[a-zA-Z0-9]+]] = sub i32 [[t1]], [[bump]] 78 ; CHECK: [[t3:%[a-zA-Z0-9]+]] = sub i32 [[t2]], [[bump]] [all …]
/external/icu/icu4c/source/test/testdata/
D	regextst.txt	1442 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1443 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1444 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1445 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1446 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1447 "^([a-zA-Z0-9_\-\.]+)@((\[[0-9]{1,3}\.[0-9]{1,3}\.[0-9]{1,3}\.)\|(([a-zA-Z0-9\-]+\.)+))([a-zA-Z]{2,4… 1557 "^(http\|https\|ftp)\://[a-zA-Z0-9\-\.]+\.[a-zA-Z]{2,3}(:[a-zA-Z0-9])?/?([a-zA-Z0-9\-\._\?\,\'/\\\+\… 1558 "^(http\|https\|ftp)\://[a-zA-Z0-9\-\.]+\.[a-zA-Z]{2,3}(:[a-zA-Z0-9])?/?([a-zA-Z0-9\-\._\?\,\'/\\\+\… 1559 "^(http\|https\|ftp)\://[a-zA-Z0-9\-\.]+\.[a-zA-Z]{2,3}(:[a-zA-Z0-9])?/?([a-zA-Z0-9\-\._\?\,\'/\\\+\… 1560 "^(http\|https\|ftp)\://[a-zA-Z0-9\-\.]+\.[a-zA-Z]{2,3}(:[a-zA-Z0-9])?/?([a-zA-Z0-9\-\._\?\,\'/\\\+\… [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Assembler/
D	auto_upgrade_nvvm_intrinsics.ll	36 ; CHECK: [[clz:%[a-zA-Z0-9.]+]] = call i64 @llvm.ctlz.i64(i64 %b, i1 false) 43 ; CHECK: [[popc:%[a-zA-Z0-9.]+]] = call i64 @llvm.ctpop.i64(i64 %b) 54 ; CHECK-DAG: [[negi:%[a-zA-Z0-9.]+]] = sub i32 0, %a 55 ; CHECK-DAG: [[cmpi:%[a-zA-Z0-9.]+]] = icmp sge i32 %a, 0 59 ; CHECK-DAG: [[negll:%[a-zA-Z0-9.]+]] = sub i64 0, %b 60 ; CHECK-DAG: [[cmpll:%[a-zA-Z0-9.]+]] = icmp sge i64 %b, 0 69 ; CHECK: [[maxi:%[a-zA-Z0-9.]+]] = icmp sge i32 %a1, %a2 73 ; CHECK: [[maxll:%[a-zA-Z0-9.]+]] = icmp sge i64 %b1, %b2 77 ; CHECK: [[maxui:%[a-zA-Z0-9.]+]] = icmp uge i32 %a1, %a2 81 ; CHECK: [[maxull:%[a-zA-Z0-9.]+]] = icmp uge i64 %b1, %b2 [all …]
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
D	split-gep.ll	27 …ementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1 46 … float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} 47 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 32 67 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 92 …TR_1:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 94 …TR_2:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 112 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 127 …ECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2… 146 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 8 156 ; CHECK: %[[j2:[a-zA-Z0-9]+]] = sub i64 0, %j [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SeparateConstOffsetFromGEP/NVPTX/
D	split-gep.ll	23 …ementptr [1024 x %struct.S], [1024 x %struct.S]* @struct_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i32 1 42 … float]], [32 x [32 x float]]* @float_2d_array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} 43 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 32 63 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 88 …TR_1:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 90 …TR_2:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 108 …_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2d_array, i6… 123 …ECK: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [32 x [32 x float]], [32 x [32 x float]]* @float_2… 142 ; CHECK: getelementptr inbounds float, float* %{{[a-zA-Z0-9]+}}, i64 8 152 ; CHECK: %[[j2:[a-zA-Z0-9]+]] = sub i64 0, %j [all …]
/external/llvm/test/Transforms/LoopVectorize/
D	if-pred-stores.ll	65 ; UNROLL: %[[IND:[a-zA-Z0-9]+]] = add i64 %{{.}}, 0 66 ; UNROLL: %[[IND1:[a-zA-Z0-9]+]] = add i64 %{{.}}, 1 67 ; UNROLL: %[[v0:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND]] 68 ; UNROLL: %[[v1:[a-zA-Z0-9]+]] = getelementptr inbounds i32, i32* %f, i64 %[[IND1]] 69 ; UNROLL: %[[v2:[a-zA-Z0-9]+]] = load i32, i32* %[[v0]], align 4 70 ; UNROLL: %[[v3:[a-zA-Z0-9]+]] = load i32, i32* %[[v1]], align 4 71 ; UNROLL: %[[v4:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v2]], 100 72 ; UNROLL: %[[v5:[a-zA-Z0-9]+]] = icmp sgt i32 %[[v3]], 100 73 ; UNROLL: %[[v6:[a-zA-Z0-9]+]] = add nsw i32 %[[v2]], 20 74 ; UNROLL: %[[v7:[a-zA-Z0-9]+]] = add nsw i32 %[[v3]], 20 [all …]
/external/llvm/test/CodeGen/PowerPC/
D	ppc64-gep-opt.ll	33 ; CHECK-NoAA: [[PTR0:%[a-zA-Z0-9]+]] = ptrtoint [240 x %struct]* %string to i64 34 ; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 35 ; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]] 45 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8* 46 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 47 ; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]] 84 ; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528 87 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 532 89 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 528 92 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr [all …]
D	ppc64-toc.ll	`63 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 65 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 67 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 69 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
D	ppc64-toc.ll	`63 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 65 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 67 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}} 69 ; CHECK-NEXT: .tc {{[\._a-zA-Z0-9]+}}[TC],{{[\._a-zA-Z0-9]+}}`
D	tail-dup-branch-to-fallthrough.ll	`16 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} 18 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} 20 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} 22 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} 24 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} 26 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}} 28 ; CHECK-NOT: # %{{[-_a-zA-Z0-9]+}}`
D	xray-conditional-return.ll	`6 ; CHECK-NEXT: ble [[CR]], [[LABEL:\.[a-zA-Z0-9]+]] 8 ; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: 23 ; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: 43 ; CHECK-NEXT: bge [[CR]], [[LABEL:\.[a-zA-Z0-9]+]] 45 ; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: 60 ; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:`
/external/llvm/test/CodeGen/AArch64/
D	aarch64-gep-opt.ll	42 ; CHECK-NoAA: [[PTR0:%[a-zA-Z0-9]+]] = ptrtoint [240 x %struct]* %string to i64 43 ; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 44 ; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]] 54 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8* 55 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 56 ; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]] 96 ; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528 99 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 532 101 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 528 104 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr [all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
D	aarch64-gep-opt.ll	42 ; CHECK-NoAA: [[PTR0:%[a-zA-Z0-9]+]] = ptrtoint [240 x %struct]* %string to i64 43 ; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 44 ; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]] 54 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8* 55 ; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 56 ; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8, i8* [[PTR0]], i64 [[IDX]] 96 ; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528 101 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, {{.}}, i64 532 105 ; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8, {{.}}, i64 528 108 ; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr [all …]
/external/llvm/test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/
D	split-gep-and-gvn-addrspace-addressing-modes.ll	8 …zA-Z0-9]+]] = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(2)* @a… 40 …-zA-Z0-9]+]] = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(2)* @ar… 43 …]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} 44 …]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} 73 …A-Z0-9]+]] = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(3)* @lds_…
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D	switch-lower-peel-top-case.ll	`18 ; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}: 23 ; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}: 33 ; CHECK: [[BB4_LABEL:.*]].{{[a-zA-Z0-9.]+}}: 38 ; CHECK: [[BB2_LABEL]].{{[a-zA-Z0-9.]+}}: 81 ; CHECK: [[PEELED_SWITCH_LABEL]].{{[a-zA-Z0-9.]+}}: 86 ; CHECK: [[BB1_LABEL]].{{[a-zA-Z0-9.]+}}: 91 ; CHECK: [[BB3_LABEL]].{{[a-zA-Z0-9.]+}}: 96 ; CHECK: [[BB2_LABEL]].{{[a-zA-Z0-9.]+}}: 101 ; CHECK: [[BB4_LABEL]].{{[a-zA-Z0-9.]+}}: 106 ; CHECK: [[BB5_LABEL]].{{[a-zA-Z0-9.]+}}:`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/XCore/
D	exception.ll	`43 ; CHECK-NEXT: [[START:.L[a-zA-Z0-9_]+]] 46 ; CHECK: .cfi_lsda 0, [[LSDA:.L[a-zA-Z0-9_]+]] 60 ; CHECK: [[PRE_G:.L[a-zA-Z0-9_]+]] 62 ; CHECK: [[POST_G:.L[a-zA-Z0-9_]+]] 63 ; CHECK: [[RETURN:.L[a-zA-Z0-9_]+]] 72 ; CHECK: {{.L[a-zA-Z0-9_]+}} 73 ; CHECK: [[LANDING:.L[a-zA-Z0-9_]+]] 95 ; CHECK: [[END:.L[a-zA-Z0-9_]+]]`
/external/llvm/test/CodeGen/XCore/
D	exception.ll	`43 ; CHECK-NEXT: [[START:.L[a-zA-Z0-9_]+]] 46 ; CHECK: .cfi_lsda 0, [[LSDA:.L[a-zA-Z0-9_]+]] 60 ; CHECK: [[PRE_G:.L[a-zA-Z0-9_]+]] 62 ; CHECK: [[POST_G:.L[a-zA-Z0-9_]+]] 63 ; CHECK: [[RETURN:.L[a-zA-Z0-9_]+]] 72 ; CHECK: {{.L[a-zA-Z0-9_]+}} 73 ; CHECK: [[LANDING:.L[a-zA-Z0-9_]+]] 95 ; CHECK: [[END:.L[a-zA-Z0-9_]+]]`

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