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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/AMDGPU/
Damdgcn-intrinsics.ll4 ; llvm.amdgcn.rcp
7 declare float @llvm.amdgcn.rcp.f32(float) nounwind readnone
8 declare double @llvm.amdgcn.rcp.f64(double) nounwind readnone
13 %val = call float @llvm.amdgcn.rcp.f32(float undef) nounwind readnone
20 %val = call float @llvm.amdgcn.rcp.f32(float 1.0) nounwind readnone
27 %val = call double @llvm.amdgcn.rcp.f64(double 1.0) nounwind readnone
34 %val = call float @llvm.amdgcn.rcp.f32(float 0.5) nounwind readnone
41 %val = call double @llvm.amdgcn.rcp.f64(double 0.5) nounwind readnone
46 ; CHECK-NEXT: call float @llvm.amdgcn.rcp.f32(float 4.300000e+01)
48 %val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) nounwind readnone
[all …]
Damdgcn-demanded-vector-elts.ll4 ; llvm.amdgcn.buffer.load
8 ; CHECK-NEXT: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, …
11 …%data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 false, i1 …
16 ; CHECK-NEXT: %data = call <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32> %rsrc, i32 %idx, i3…
19 …%data = call <1 x float> @llvm.amdgcn.buffer.load.v1f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 fa…
24 ; CHECK-NEXT: %data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i3…
27 …%data = call <2 x float> @llvm.amdgcn.buffer.load.v2f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 fa…
32 ; CHECK-NEXT: %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i3…
35 …%data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 fa…
40 ; CHECK: %data = call float @llvm.amdgcn.buffer.load.f32(<4 x i32> %rsrc, i32 %idx, i32 %ofs, i1 fa…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.incperflevel.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 declare void @llvm.amdgcn.s.incperflevel(i32) #0
24 call void @llvm.amdgcn.s.incperflevel(i32 0)
25 call void @llvm.amdgcn.s.incperflevel(i32 1)
26 call void @llvm.amdgcn.s.incperflevel(i32 2)
27 call void @llvm.amdgcn.s.incperflevel(i32 3)
28 call void @llvm.amdgcn.s.incperflevel(i32 4)
29 call void @llvm.amdgcn.s.incperflevel(i32 5)
30 call void @llvm.amdgcn.s.incperflevel(i32 6)
[all …]
Dllvm.amdgcn.s.sleep.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 declare void @llvm.amdgcn.s.sleep(i32) #0
24 call void @llvm.amdgcn.s.sleep(i32 0)
25 call void @llvm.amdgcn.s.sleep(i32 1)
26 call void @llvm.amdgcn.s.sleep(i32 2)
27 call void @llvm.amdgcn.s.sleep(i32 3)
28 call void @llvm.amdgcn.s.sleep(i32 4)
29 call void @llvm.amdgcn.s.sleep(i32 5)
30 call void @llvm.amdgcn.s.sleep(i32 6)
[all …]
Dllvm.amdgcn.s.decperflevel.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 declare void @llvm.amdgcn.s.decperflevel(i32) #0
24 call void @llvm.amdgcn.s.decperflevel(i32 0)
25 call void @llvm.amdgcn.s.decperflevel(i32 1)
26 call void @llvm.amdgcn.s.decperflevel(i32 2)
27 call void @llvm.amdgcn.s.decperflevel(i32 3)
28 call void @llvm.amdgcn.s.decperflevel(i32 4)
29 call void @llvm.amdgcn.s.decperflevel(i32 5)
30 call void @llvm.amdgcn.s.decperflevel(i32 6)
[all …]
Dzext-lid.ll1 ; RUN: llc -march=amdgcn < %s | FileCheck %s
2 ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-lower-intrinsics < %s | FileCheck -check-prefix=OPT %s
7 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
8 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !0
9 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.z(), !range !0
12 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
15 %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.y()
19 %tmp5 = tail call i32 @llvm.amdgcn.workitem.id.z()
27 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.x(), !range !2
28 ; OPT: tail call i32 @llvm.amdgcn.workitem.id.y(), !range !3
[all …]
Dhsa-note-no-func.ll1 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx600 | FileCheck --check-prefix=HSA --check-prefix=…
2 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx601 | FileCheck --check-prefix=HSA --check-prefix=…
3 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx700 | FileCheck --check-prefix=HSA --check-prefix=…
4 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx701 | FileCheck --check-prefix=HSA --check-prefix=…
5 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx702 | FileCheck --check-prefix=HSA --check-prefix=…
6 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx703 | FileCheck --check-prefix=HSA --check-prefix=…
7 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=gfx704 | FileCheck --check-prefix=HSA --check-prefix=…
8 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=bonaire | FileCheck --check-prefix=HSA --check-prefix…
9 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=mullins | FileCheck --check-prefix=HSA --check-prefix…
10 ; RUN: llc < %s -mtriple=amdgcn--amdhsa -mcpu=hawaii | FileCheck --check-prefix=HSA --check-prefix=…
[all …]
Dllvm.amdgcn.interp.ll1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-o…
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-o…
3 ; RUN: llc -march=amdgcn -mcpu=kabini -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-…
4 ; RUN: llc -march=amdgcn -mcpu=stoney -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-…
17 %p0_0 = call float @llvm.amdgcn.interp.p1(float %i, i32 0, i32 0, i32 %arg3)
18 %p1_0 = call float @llvm.amdgcn.interp.p2(float %p0_0, float %j, i32 0, i32 0, i32 %arg3)
19 %p0_1 = call float @llvm.amdgcn.interp.p1(float %i, i32 1, i32 0, i32 %arg3)
20 %p1_1 = call float @llvm.amdgcn.interp.p2(float %p0_1, float %j, i32 1, i32 0, i32 %arg3)
21 %const = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %arg3)
23 …call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %p0_0, float %p0_0, float %p1_1, float %w, i1 …
[all …]
Dfence-barrier.ll1 ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --…
2 ; RUN: llvm-as -data-layout=A5 < %s | llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -verify-ma…
4 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
5 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
6 declare i32 @llvm.amdgcn.workitem.id.x()
7 declare i32 @llvm.amdgcn.workgroup.id.x()
8 declare void @llvm.amdgcn.s.barrier()
22 %3 = call i32 @llvm.amdgcn.workitem.id.x()
33 call void @llvm.amdgcn.s.barrier()
37 %10 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
[all …]
Dannotate-kernel-features-hsa.ll1 ; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -che…
3 declare i32 @llvm.amdgcn.workgroup.id.x() #0
4 declare i32 @llvm.amdgcn.workgroup.id.y() #0
5 declare i32 @llvm.amdgcn.workgroup.id.z() #0
7 declare i32 @llvm.amdgcn.workitem.id.x() #0
8 declare i32 @llvm.amdgcn.workitem.id.y() #0
9 declare i32 @llvm.amdgcn.workitem.id.z() #0
11 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
12 declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
13 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
[all …]
Dllvm.amdgcn.buffer.atomic.ll1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -…
2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -…
23 %o1 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
24 %o2 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
25 …%o3 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0)
26 …%o4 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %voffset…
28 %o5 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0)
29 %o6 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0)
30 %unused = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o6, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
56 …%t1 = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
[all …]
Dllvm.amdgcn.buffer.load.ll1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -…
2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -…
11 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
12 …%data_glc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
13 …%data_slc = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
25 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 40, i1 0, i1 0)
36 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 8192, i1 0, i1 0)
45 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 %1, i32 0, i1 0, i1 0)
54 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %1, i1 0, i1 0)
64 %data = call <4 x float> @llvm.amdgcn.buffer.load.v4f32(<4 x i32> %0, i32 0, i32 %ofs, i1 0, i1 0)
[all …]
Dllvm.amdgcn.buffer.store.ll1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=VERDE %s
2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
11 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 0, i1 0, i1 0)
12 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %2, <4 x i32> %0, i32 0, i32 0, i1 1, i1 0)
13 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %3, <4 x i32> %0, i32 0, i32 0, i1 0, i1 1)
22 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 42, i1 0, i1 0)
31 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 0, i1 0, i1 0)
40 call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 0, i32 %2, i1 0, i1 0)
49 …call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %2, i32 %3, i1 0, i1 0)
59 …call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %1, <4 x i32> %0, i32 %3, i32 %2, i1 0, i1 0)
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.s.sleep.ll1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
4 declare void @llvm.amdgcn.s.sleep(i32) #0
24 call void @llvm.amdgcn.s.sleep(i32 0)
25 call void @llvm.amdgcn.s.sleep(i32 1)
26 call void @llvm.amdgcn.s.sleep(i32 2)
27 call void @llvm.amdgcn.s.sleep(i32 3)
28 call void @llvm.amdgcn.s.sleep(i32 4)
29 call void @llvm.amdgcn.s.sleep(i32 5)
30 call void @llvm.amdgcn.s.sleep(i32 6)
[all …]
Dllvm.amdgcn.buffer.atomic.ll1 ;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -…
2 ;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK -…
22 %o1 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
23 %o2 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o1, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
24 …%o3 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o2, <4 x i32> %rsrc, i32 0, i32 %voffset, i1 0)
25 …%o4 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o3, <4 x i32> %rsrc, i32 %vindex, i32 %voffset…
27 %o5 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o4, <4 x i32> %rsrc, i32 0, i32 %ofs.5, i1 0)
28 %o6 = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o5, <4 x i32> %rsrc, i32 0, i32 8192, i1 0)
29 %unused = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %o6, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
54 …%t1 = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
[all …]
Dannotate-kernel-features-hsa.ll1 ; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -che…
3 declare i32 @llvm.amdgcn.workgroup.id.x() #0
4 declare i32 @llvm.amdgcn.workgroup.id.y() #0
5 declare i32 @llvm.amdgcn.workgroup.id.z() #0
7 declare i32 @llvm.amdgcn.workitem.id.x() #0
8 declare i32 @llvm.amdgcn.workitem.id.y() #0
9 declare i32 @llvm.amdgcn.workitem.id.z() #0
11 declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
12 declare i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0
16 %val = call i32 @llvm.amdgcn.workgroup.id.x()
[all …]
/external/llvm/test/Transforms/InstCombine/
Damdgcn-intrinsics.ll4 ; llvm.amdgcn.rcp
7 declare float @llvm.amdgcn.rcp.f32(float) nounwind readnone
8 declare double @llvm.amdgcn.rcp.f64(double) nounwind readnone
14 %val = call float @llvm.amdgcn.rcp.f32(float 1.0) nounwind readnone
21 %val = call double @llvm.amdgcn.rcp.f64(double 1.0) nounwind readnone
28 %val = call float @llvm.amdgcn.rcp.f32(float 0.5) nounwind readnone
35 %val = call double @llvm.amdgcn.rcp.f64(double 0.5) nounwind readnone
40 ; CHECK-NEXT: call float @llvm.amdgcn.rcp.f32(float 4.300000e+01)
42 %val = call float @llvm.amdgcn.rcp.f32(float 4.300000e+01) nounwind readnone
47 ; CHECK-NEXT: call double @llvm.amdgcn.rcp.f64(double 4.300000e+01)
[all …]
/external/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
Dllvm.amdgcn.buffer.atomic.ll1 ;RUN: opt -mtriple=amdgcn-mesa-mesa3d -analyze -divergence %s | FileCheck %s
3 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.swap(
6 %orig = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
11 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.add(
14 %orig = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
19 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.sub(
22 %orig = call i32 @llvm.amdgcn.buffer.atomic.sub(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
27 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.smin(
30 %orig = call i32 @llvm.amdgcn.buffer.atomic.smin(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
35 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.umin(
[all …]
Dllvm.amdgcn.image.atomic.ll1 ;RUN: opt -mtriple=amdgcn-mesa-mesa3d -analyze -divergence %s | FileCheck %s
3 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.swap.i32(
6 …%orig = call i32 @llvm.amdgcn.image.atomic.swap.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i1 0, i…
11 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.add.i32(
14 …%orig = call i32 @llvm.amdgcn.image.atomic.add.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i1 0, i1…
19 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.sub.i32(
22 …%orig = call i32 @llvm.amdgcn.image.atomic.sub.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i1 0, i1…
27 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.smin.i32(
30 …%orig = call i32 @llvm.amdgcn.image.atomic.smin.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i1 0, i…
35 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.umin.i32(
[all …]
Dworkitem-intrinsics.ll1 ; RUN: opt -mtriple amdgcn-unknown-amdhsa -analyze -divergence %s | FileCheck %s
3 declare i32 @llvm.amdgcn.workitem.id.x() #0
4 declare i32 @llvm.amdgcn.workitem.id.y() #0
5 declare i32 @llvm.amdgcn.workitem.id.z() #0
6 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
7 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
9 ; CHECK: DIVERGENT: %id.x = call i32 @llvm.amdgcn.workitem.id.x()
11 %id.x = call i32 @llvm.amdgcn.workitem.id.x()
16 ; CHECK: DIVERGENT: %id.y = call i32 @llvm.amdgcn.workitem.id.y()
18 %id.y = call i32 @llvm.amdgcn.workitem.id.y()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/DivergenceAnalysis/AMDGPU/
Dllvm.amdgcn.buffer.atomic.ll1 ;RUN: opt -mtriple=amdgcn-mesa-mesa3d -analyze -divergence %s | FileCheck %s
3 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.swap(
6 %orig = call i32 @llvm.amdgcn.buffer.atomic.swap(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
11 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.add(
14 %orig = call i32 @llvm.amdgcn.buffer.atomic.add(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
19 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.sub(
22 %orig = call i32 @llvm.amdgcn.buffer.atomic.sub(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
27 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.smin(
30 %orig = call i32 @llvm.amdgcn.buffer.atomic.smin(i32 %data, <4 x i32> %rsrc, i32 0, i32 0, i1 0)
35 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.buffer.atomic.umin(
[all …]
Dllvm.amdgcn.image.atomic.ll1 ;RUN: opt -mtriple=amdgcn-mesa-mesa3d -analyze -divergence %s | FileCheck %s
3 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(
6 …%orig = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, …
11 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(
14 …%orig = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i…
19 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i32(
22 …%orig = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, i…
27 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i32(
30 …%orig = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i32(i32 %data, i32 %addr, <8 x i32> %rsrc, …
35 ;CHECK: DIVERGENT: %orig = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i32(
[all …]
Dworkitem-intrinsics.ll1 ; RUN: opt -mtriple amdgcn-unknown-amdhsa -analyze -divergence %s | FileCheck %s
3 declare i32 @llvm.amdgcn.workitem.id.x() #0
4 declare i32 @llvm.amdgcn.workitem.id.y() #0
5 declare i32 @llvm.amdgcn.workitem.id.z() #0
6 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
7 declare i32 @llvm.amdgcn.mbcnt.hi(i32, i32) #0
9 ; CHECK: DIVERGENT: %id.x = call i32 @llvm.amdgcn.workitem.id.x()
11 %id.x = call i32 @llvm.amdgcn.workitem.id.x()
16 ; CHECK: DIVERGENT: %id.y = call i32 @llvm.amdgcn.workitem.id.y()
18 %id.y = call i32 @llvm.amdgcn.workitem.id.y()
[all …]
/external/clang/test/CodeGenOpenCL/
Dbuiltins-amdgcn.cl2 // RUN: %clang_cc1 -triple amdgcn-unknown-unknown -S -emit-llvm -o - %s | FileCheck %s
9 // CHECK: call { double, i1 } @llvm.amdgcn.div.scale.f64(double %a, double %b, i1 true)
22 // CHECK: call { float, i1 } @llvm.amdgcn.div.scale.f32(float %a, float %b, i1 true)
35 // CHECK: call float @llvm.amdgcn.div.fmas.f32
42 // CHECK: call double @llvm.amdgcn.div.fmas.f64
49 // CHECK: call float @llvm.amdgcn.div.fixup.f32
56 // CHECK: call double @llvm.amdgcn.div.fixup.f64
63 // CHECK: call float @llvm.amdgcn.trig.preop.f32
70 // CHECK: call double @llvm.amdgcn.trig.preop.f64
77 // CHECK: call float @llvm.amdgcn.rcp.f32
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dhsa-v3.s187 .byte .amdgcn.gfx_generation_number
190 .byte .amdgcn.next_free_vgpr
192 .byte .amdgcn.next_free_sgpr
197 .byte .amdgcn.next_free_vgpr
199 .byte .amdgcn.next_free_sgpr
202 .set .amdgcn.next_free_vgpr, 0
203 .set .amdgcn.next_free_sgpr, 0
205 .byte .amdgcn.next_free_vgpr
207 .byte .amdgcn.next_free_sgpr
212 .byte .amdgcn.next_free_vgpr
[all …]

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