Searched refs:b0101 (Results 1 – 25 of 43) sorted by relevance
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127 def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>;128 def : IC<"IVAU", 0b011, 0b0111, 0b0101, 0b001, 1>;399 def : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>;400 def : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>;401 def : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>;402 def : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>;413 def : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>;414 def : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>;419 def : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;420 def : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;[all …]
133 defm FMINNM_ZPmZ : sve_fp_2op_p_zds<0b0101, "fminnm">;255 def BICS_PPzPP : sve_int_pred_log<0b0101, "bics">;284 defm LD1H_IMM : sve_mem_cld_si<0b0101, "ld1h", Z_h, ZPR16>;330 defm LD1H : sve_mem_cld_ss<0b0101, "ld1h", Z_h, ZPR16, GPR64NoXZRshifted16>;348 defm LDNF1H_IMM : sve_mem_cldnf_si<0b0101, "ldnf1h", Z_h, ZPR16>;366 defm LDFF1H : sve_mem_cldff_ss<0b0101, "ldff1h", Z_h, ZPR16, GPR64shifted16>;413 defm GLDFF1SH_S : sve_mem_32b_gld_vs_32_unscaled<0b0101, "ldff1sh", ZPR32ExtSXTW8, ZPR32ExtUXTW8>;422 defm GLDFF1SH_S : sve_mem_32b_gld_sv_32_scaled<0b0101, "ldff1sh", ZPR32ExtSXTW16, ZPR32ExtUXTW16>;435 defm GLDFF1SH_S : sve_mem_32b_gld_vi_32_ptrs<0b0101, "ldff1sh", uimm5s2>;448 defm GLDFF1SH_D : sve_mem_64b_gld_vi_64_ptrs<0b0101, "ldff1sh", uimm5s2>;[all …]
122 def : IC<"IALLU", 0b000, 0b0111, 0b0101, 0b000, 0>;313 def : ROSysReg<"DBGDTRRX_EL0", 0b10, 0b011, 0b0000, 0b0101, 0b000>;343 def : ROSysReg<"ID_AA64DFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b000>;344 def : ROSysReg<"ID_AA64DFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b001>;345 def : ROSysReg<"ID_AA64AFR0_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b100>;346 def : ROSysReg<"ID_AA64AFR1_EL1", 0b11, 0b000, 0b0000, 0b0101, 0b101>;373 def : ROSysReg<"TRCIDR13", 0b10, 0b001, 0b0000, 0b0101, 0b110>;383 def : ROSysReg<"TRCPDSR", 0b10, 0b001, 0b0001, 0b0101, 0b100>;392 def : ROSysReg<"TRCPIDR5", 0b10, 0b001, 0b0111, 0b0101, 0b111>;423 def : ROSysReg<"ERRIDR_EL1", 0b11, 0b000, 0b0101, 0b0011, 0b000>;[all …]
84 let IClass = 0b0101;108 let IClass = 0b0101;125 let IClass = 0b0101;
455 class V6_vS32b_new_npred_ai_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai<0b0101>;472 class V6_vS32b_new_npred_ai_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ai_128B<0b0101>;642 class V6_vS32b_new_npred_pi_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi<0b0101>;659 class V6_vS32b_new_npred_pi_128B_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_pi_128B<0b0101>;737 class V6_vS32b_new_npred_ppu_enc : Enc_COPROC_VMEM_vS32b_n_ew_pred_ppu<0b0101>;824 class V6_vasrwuhsat_enc : Enc_COPROC_VX_4op_r<0b0101>;
34 let IClass = 0b0101;53 let IClass = 0b0101;
82 let Inst{27-24} = 0b0101;991 def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;1451 let IClass = 0b0101;1473 let IClass = 0b0101;1510 let IClass = 0b0101;1529 let IClass = 0b0101;1567 let IClass = 0b0101;1749 def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;1948 def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;2023 def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;[all …]
516 let Inst{12-9} = 0b0101;
45 int b = 0b0101;
10 def c0 : C<[0b0101, 0b1010]>;
172 let IClass = 0b0101;194 let IClass = 0b0101;227 let IClass = 0b0101;287 let IClass = 0b0101;344 let IClass = 0b0101;
280 defm : int_cond_alias<"cs", 0b0101>;292 defm : int_cond_alias<"lu", 0b0101>; // same as cs298 defm : fp_cond_alias<"ug", 0b0101>;321 defm : cp_cond_alias<"23", 0b0101>;
460 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;461 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;462 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;463 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;464 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;465 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;666 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {678 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {702 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {713 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {[all …]
323 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,331 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,344 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,352 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
942 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;943 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;944 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;945 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;946 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;947 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;1147 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {1159 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {1183 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {1194 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {[all …]
566 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,574 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,586 def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,595 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,603 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,615 def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,2092 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
2119 let Inst{26-23} = 0b0101;2151 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">;2152 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;2153 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;2154 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">;2155 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;2156 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">;3282 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),3357 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
964 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;965 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;966 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;967 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;968 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;969 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;1187 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {1199 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {1223 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {1234 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {[all …]
579 def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,587 def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,599 def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,607 def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,615 def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,627 def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,2261 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPRnopc:$Rt), (ins),
2175 let Inst{26-23} = 0b0101;2203 def t2UQSUB8 : T2I_pam_intrinsics<0b100, 0b0101, "uqsub8", int_arm_uqsub8>;2207 def t2UQADD16 : T2I_pam_intrinsics<0b001, 0b0101, "uqadd16", int_arm_uqadd16>;2208 def t2UQADD8 : T2I_pam_intrinsics<0b000, 0b0101, "uqadd8", int_arm_uqadd8>;2209 def t2UQASX : T2I_pam_intrinsics<0b010, 0b0101, "uqasx", int_arm_uqasx>;2210 def t2UQSAX : T2I_pam_intrinsics<0b110, 0b0101, "uqsax", int_arm_uqsax>;2211 def t2UQSUB16 : T2I_pam_intrinsics<0b101, 0b0101, "uqsub16", int_arm_uqsub16>;3264 def t2LDREXH : T2I_ldrex<0b0101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),3339 def t2STREXH : T2I_strex<0b0101, (outs rGPR:$Rd),
132 b0101 = 0x5, enumerator152 { true, true, false, b1010, b1010, b0101, false, NONE },
664 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;665 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;723 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;724 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;833 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;834 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;835 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;836 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;851 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;852 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
662 class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;663 class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;721 class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;722 class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;831 class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;832 class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;833 class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;834 class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;849 class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;850 class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;