Searched refs:brw_load_register_imm32 (Results 1 – 11 of 11) sorted by relevance
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | gen8_multisample_state.c | 61 brw_load_register_imm32(brw, GEN7_CACHE_MODE_0, 0); in gen10_emit_wa_lri_to_cache_mode_zero()
|
| D | brw_state_upload.c | 66 brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS, in brw_upload_initial_gpu_state()
89 brw_load_register_imm32(brw, GEN7_CACHE_MODE_1, in brw_upload_initial_gpu_state()
96 brw_load_register_imm32(brw, GEN7_GT_MODE, in brw_upload_initial_gpu_state()
|
| D | gen7_sol_state.c | 57 brw_load_register_imm32(brw, GEN7_SO_WRITE_OFFSET(i), 0); in gen7_begin_transform_feedback()
|
| D | hsw_sol.c | 93 brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0); in tally_prims_written()
|
| D | gen8_depth_state.c | 334 brw_load_register_imm32(brw, GEN7_CACHE_MODE_1, in gen8_write_pma_stall_bits()
|
| D | gen7_l3_state.c | 131 brw_load_register_imm32(brw, GEN8_L3CNTLREG, imm_data); in setup_l3_config()
|
| D | hsw_queryobj.c | 158 brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0); in shr_gpr0_by_2_bits()
|
| D | brw_draw.c | 246 brw_load_register_imm32(brw, GEN7_3DPRIM_BASE_VERTEX, 0); in brw_emit_prim()
985 brw_load_register_imm32(brw, MI_PREDICATE_SRC0 + 4, 0); in brw_draw_prims()
|
| D | brw_misc_state.c | 531 brw_load_register_imm32(brw, SLICE_COMMON_ECO_CHICKEN1, in brw_emit_select_pipeline()
|
| D | brw_context.h | 1393 void brw_load_register_imm32(struct brw_context *brw,
|
| D | intel_batchbuffer.c | 1307 brw_load_register_imm32(struct brw_context *brw, uint32_t reg, uint32_t imm) in brw_load_register_imm32() function
|