| /external/u-boot/drivers/net/fsl-mc/dpio/ |
| D | qbman_portal.h | 128 const uint32_t *cacheline) in qb_attr_code_decode() argument
130 return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]); in qb_attr_code_decode()
136 uint32_t *cacheline, uint32_t val) in qb_attr_code_encode() argument
138 cacheline[code->word] = in qb_attr_code_encode()
139 r32_uint32_t(code->lsoffset, code->width, cacheline[code->word]) in qb_attr_code_encode()
144 uint64_t *cacheline, uint64_t val) in qb_attr_code_encode_64() argument
146 cacheline[code->word / 2] = val; in qb_attr_code_encode_64()
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| /external/mesa3d/src/gallium/auxiliary/util/ |
| D | u_cpu_detect.c | 398 util_cpu_caps.cacheline = sizeof(void *); in util_cpu_detect()
405 util_cpu_caps.cacheline = 32; in util_cpu_detect()
411 unsigned int cacheline; in util_cpu_detect() local
442 cacheline = ((regs2[1] >> 8) & 0xFF) * 8; in util_cpu_detect()
443 if (cacheline > 0) in util_cpu_detect()
444 util_cpu_caps.cacheline = cacheline; in util_cpu_detect()
491 unsigned int cacheline; in util_cpu_detect() local
493 cacheline = regs2[2] & 0xFF; in util_cpu_detect()
494 if (cacheline > 0) in util_cpu_detect()
495 util_cpu_caps.cacheline = cacheline; in util_cpu_detect()
[all …]
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| D | u_cpu_detect.h | 53 unsigned cacheline; member
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| /external/virglrenderer/src/gallium/auxiliary/util/ |
| D | u_cpu_detect.c | 338 util_cpu_caps.cacheline = sizeof(void *); in util_cpu_detect()
345 util_cpu_caps.cacheline = 32; in util_cpu_detect()
351 unsigned int cacheline; in util_cpu_detect() local
381 cacheline = ((regs2[1] >> 8) & 0xFF) * 8; in util_cpu_detect()
382 if (cacheline > 0) in util_cpu_detect()
383 util_cpu_caps.cacheline = cacheline; in util_cpu_detect()
413 util_cpu_caps.cacheline = regs2[2] & 0xFF; in util_cpu_detect()
434 debug_printf("util_cpu_caps.cacheline = %u\n", util_cpu_caps.cacheline); in util_cpu_detect()
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| D | u_cpu_detect.h | 53 unsigned cacheline; member
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | r600.func-alignment.ll | 5 ; Functions need to be cacheline (256B) aligned to prevent GPU hangs
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| /external/u-boot/doc/ |
| D | README.fsl-ddr | 70 # cacheline interleaving
71 setenv hwconfig "fsl_ddr:ctlr_intlv=cacheline"
152 hwconfig=fsl_ddr:addr_hash=true,ctlr_intlv=cacheline,bank_intlv=cs0_cs1_cs2_cs3,ecc=on
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonSystemInst.td | 93 // Zero an aligned 32-byte cacheline.
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| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| D | lp_texture.c | 86 unsigned mip_align = MAX2(64, util_cpu_caps.cacheline); in llvmpipe_texture_layout()
124 lpr->row_stride[level] = align(nblocksx * block_size, util_cpu_caps.cacheline); in llvmpipe_texture_layout()
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| /external/u-boot/include/configs/ |
| D | T4240QDS.h | 513 #define CTRL_INTLV_PREFERED cacheline
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| D | T4240RDB.h | 661 #define CTRL_INTLV_PREFERED cacheline
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| D | T208xRDB.h | 196 #define CTRL_INTLV_PREFERED cacheline
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| D | T208xQDS.h | 212 #define CTRL_INTLV_PREFERED cacheline
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| /external/jemalloc/include/jemalloc/internal/ |
| D | jemalloc_internal.h.in | 310 * In addition, this controls the spacing of cacheline-spaced size classes.
319 /* Return the smallest cacheline multiple that is >= s. */
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| /external/llvm/lib/Target/X86/ |
| D | README.txt | 351 Make sure the instruction which starts a loop does not cross a cacheline
355 In the new trace, the hot loop has an instruction which crosses a cacheline
358 to grab the bytes from the next cacheline.
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | README.txt | 351 Make sure the instruction which starts a loop does not cross a cacheline
355 In the new trace, the hot loop has an instruction which crosses a cacheline
358 to grab the bytes from the next cacheline.
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | README.txt | 435 Make sure the instruction which starts a loop does not cross a cacheline
439 In the new trace, the hot loop has an instruction which crosses a cacheline
442 to grab the bytes from the next cacheline.
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| /external/jemalloc/ |
| D | ChangeLog | 728 "arenas.cacheline", "arenas.subpage", "arenas.[tqcs]space_{min,max}", and
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| /external/jemalloc_new/ |
| D | ChangeLog | 1102 "arenas.cacheline", "arenas.subpage", "arenas.[tqcs]space_{min,max}", and
|