Searched refs:cctl (Results 1 – 6 of 6) sorted by relevance
| /external/u-boot/arch/arm/cpu/arm926ejs/mx25/ |
| D | generic.c | 71 ulong cctl = readl(&ccm->cctl); in imx_get_armclk() local
75 if (cctl & CCM_CCTL_ARM_SRC) in imx_get_armclk()
78 div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT) in imx_get_armclk()
87 ulong cctl = readl(&ccm->cctl); in imx_get_ahbclk() local
91 div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT) in imx_get_ahbclk()
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| /external/u-boot/arch/nds32/cpu/n1213/ |
| D | start.S | 394 cctl $p1, L1I_IX_INVAL
429 cctl $p1, L1D_IX_INVAL
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| /external/u-boot/arch/arm/lib/ |
| D | asm-offsets.c | 40 DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); in main()
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| /external/u-boot/arch/arm/include/asm/arch-mx25/ |
| D | imx-regs.h | 26 u32 cctl; /* Clock Control */ member
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_lowering_nvc0.cpp | 1622 Instruction *cctl = bld.mkOp1(OP_CCTL, TYPE_NONE, NULL, cas->getSrc(0)); in handleCasExch() local
1623 cctl->setIndirect(0, 0, cas->getIndirect(0, 0)); in handleCasExch()
1624 cctl->fixed = 1; in handleCasExch()
1625 cctl->subOp = NV50_IR_SUBOP_CCTL_IV; in handleCasExch()
1627 cctl->setPredicate(cas->cc, cas->getPredicate()); in handleCasExch()
2896 const bool cctl = i->src(0).getFile() == FILE_MEMORY_BUFFER; in visit() local
2898 handleCasExch(i, cctl); in visit()
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| /external/mesa3d/src/gallium/drivers/nouveau/codegen/lib/ |
| D | gk104.asm | 668 cctl ivall 0 l[0] label
669 cctl ivall 0 g[$r0d] label
698 cctl ivall 0 g[0] label
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