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Searched refs:cdw (Results 1 – 25 of 49) sorted by relevance

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/external/mesa3d/src/amd/vulkan/winsys/amdgpu/
Dradv_amdgpu_cs.c252 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
258 uint64_t ib_dws = MAX2(cs->base.cdw + min_size, in radv_amdgpu_cs_grow()
272 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
281 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
286 cs->old_cs_buffers[cs->num_old_cs_buffers].cdw = cs->base.cdw; in radv_amdgpu_cs_grow()
292 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
296 ib_dws = MAX2(cs->base.cdw + min_size, in radv_amdgpu_cs_grow()
312 cs->base.cdw = 0; in radv_amdgpu_cs_grow()
322 while (!cs->base.cdw || (cs->base.cdw & 7) != 4) in radv_amdgpu_cs_grow()
323 cs->base.buf[cs->base.cdw++] = 0xffff1000; in radv_amdgpu_cs_grow()
[all …]
/external/mesa3d/src/amd/vulkan/
Dradv_cs.h37 if (cs->max_dw - cs->cdw < needed) in radeon_check_space()
39 return cs->cdw + needed; in radeon_check_space()
45 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_config_reg_seq()
60 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_context_reg_seq()
78 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_context_reg_idx()
87 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_sh_reg_seq()
102 assert(cs->cdw + 2 + num <= cs->max_dw); in radeon_set_uconfig_reg_seq()
119 assert(cs->cdw + 3 <= cs->max_dw); in radeon_set_uconfig_reg_idx()
Dradv_radeon_winsys.h98 unsigned cdw; /* Number of used dwords. */ member
294 cs->buf[cs->cdw++] = value; in radeon_emit()
300 memcpy(cs->buf + cs->cdw, values, count * 4); in radeon_emit_array()
301 cs->cdw += count; in radeon_emit_array()
/external/mesa3d/src/gallium/drivers/r300/
Dr300_cs.h49 assert(size <= (cs_copy->current.max_dw - cs_copy->current.cdw)); \
75 cs_copy->current.buf[cs_copy->current.cdw++] = (value); \
99 memcpy(cs_copy->current.buf + cs_copy->current.cdw, (values), (count) * 4); \
100 cs_copy->current.cdw += (count); \
123 memcpy(cs_copy->current.buf + cs_copy->current.cdw, (values), (count) * 4); \
124 cs_copy->current.cdw += (count); \
/external/libdrm/radeon/
Dradeon_cs.h55 unsigned cdw; member
117 cs->packets[cs->cdw++] = dword; in radeon_cs_write_dword()
125 memcpy(cs->packets + cs->cdw, &qword, sizeof(uint64_t)); in radeon_cs_write_qword()
126 cs->cdw += 2; in radeon_cs_write_qword()
135 memcpy(cs->packets + cs->cdw, data, size * 4); in radeon_cs_write_table()
136 cs->cdw += size; in radeon_cs_write_table()
Dradeon_cs_gem.c296 if (cs->cdw + ndw > cs->ndw) { in cs_gem_begin()
300 tmp = (cs->cdw + ndw + 0x3FF) & (~0x3FF); in cs_gem_begin()
366 blob = bof_blob(cs->cdw * 4, cs->packets); in cs_gem_dump_bof()
431 while (cs->cdw & 7) in cs_gem_emit()
437 csg->chunks[0].length_dw = cs->cdw; in cs_gem_emit()
489 cs->cdw = 0; in cs_gem_erase()
509 for (i = 0; i < cs->cdw; i++) { in cs_gem_print()
Dradeon_cs_int.h15 unsigned cdw; member
/external/virglrenderer/tests/
Dtestvirgl_encode.h39 state->buf[state->cdw++] = dword; in virgl_encoder_write_dword()
45 memcpy(state->buf + state->cdw, &qword, sizeof(uint64_t)); in virgl_encoder_write_qword()
46 state->cdw += 2; in virgl_encoder_write_qword()
52 memcpy(state->buf + state->cdw, &qword, sizeof(double)); in virgl_encoder_write_double()
53 state->cdw += 2; in virgl_encoder_write_double()
60 memcpy(state->buf + state->cdw, ptr, len); in virgl_encoder_write_block()
64 uint8_t *mp = (uint8_t *)(state->buf + state->cdw); in virgl_encoder_write_block()
68 state->cdw += (len + 3) / 4; in virgl_encoder_write_block()
Dtestvirgl.h34 unsigned cdw; member
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_cs.h117 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()
131 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_context_reg_seq()
147 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_context_reg_idx()
156 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_sh_reg_seq()
170 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_uconfig_reg_seq()
186 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_uconfig_reg_idx()
Dradeon_winsys.h165 unsigned cdw; /* Number of used dwords. */ member
645 return cs && (cs->prev_dw + cs->current.cdw > num_dw); in radeon_emitted()
650 cs->current.buf[cs->current.cdw++] = value; in radeon_emit()
656 memcpy(cs->current.buf + cs->current.cdw, values, count * 4); in radeon_emit_array()
657 cs->current.cdw += count; in radeon_emit_array()
Dradeon_vcn_enc_1_2.c41 #define RADEON_ENC_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
43 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
48 #define RADEON_ENC_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; \
78 enc->cs->current.buf[enc->cs->current.cdw] = 0; in radeon_enc_output_one_byte()
79 …enc->cs->current.buf[enc->cs->current.cdw] |= ((unsigned int)(byte) << index_to_shifts[enc->byte_i… in radeon_enc_output_one_byte()
84 enc->cs->current.cdw++; in radeon_enc_output_one_byte()
157 enc->cs->current.cdw++; in radeon_enc_flush_headers()
207 enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_task_info()
369 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_nalu_sps()
449 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_nalu_pps()
Dr600_pipe_common.c211 assert((num_dw + ctx->dma.cs->current.cdw) <= ctx->dma.cs->current.max_dw); in si_need_dma_space()
288 saved->num_dw = cs->prev_dw + cs->current.cdw; in si_save_cs()
295 memcpy(buf, cs->prev[i].buf, cs->prev[i].cdw * 4); in si_save_cs()
296 buf += cs->prev[i].cdw; in si_save_cs()
298 memcpy(buf, cs->current.buf, cs->current.cdw * 4); in si_save_cs()
Dradeon_vce.h33 #define RVCE_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
35 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
40 #define RVCE_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; }
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h134 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_config_reg_seq()
148 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_context_reg_seq()
164 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_context_reg_idx()
173 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_sh_reg_seq()
187 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_uconfig_reg_seq()
203 assert(cs->current.cdw + 3 <= cs->current.max_dw); in radeon_set_uconfig_reg_idx()
Dradeon_vce.h39 #define RVCE_CS(value) (enc->cs->current.buf[enc->cs->current.cdw++] = (value))
41 uint32_t *begin = &enc->cs->current.buf[enc->cs->current.cdw++]; \
46 #define RVCE_END() *begin = (&enc->cs->current.buf[enc->cs->current.cdw] - begin) * 4; }
Dr600_pipe.h609 assert(cs->current.cdw + cb->num_dw <= cs->current.max_dw); in r600_emit_command_buffer()
610 memcpy(cs->current.buf + cs->current.cdw, cb->buf, 4 * cb->num_dw); in r600_emit_command_buffer()
611 cs->current.cdw += cb->num_dw; in r600_emit_command_buffer()
970 cs->current.buf[cs->current.cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE; in radeon_compute_set_context_reg_seq()
976 assert(cs->current.cdw + 2 + num <= cs->current.max_dw); in radeon_set_ctl_const_seq()
/external/mesa3d/src/gallium/drivers/virgl/
Dvirgl_encode.h57 state->buf[state->cdw++] = dword; in virgl_encoder_write_dword()
63 memcpy(state->buf + state->cdw, &qword, sizeof(uint64_t)); in virgl_encoder_write_qword()
64 state->cdw += 2; in virgl_encoder_write_qword()
71 memcpy(state->buf + state->cdw, ptr, len); in virgl_encoder_write_block()
75 uint8_t *mp = (uint8_t *)(state->buf + state->cdw); in virgl_encoder_write_block()
79 state->cdw += (len + 3) / 4; in virgl_encoder_write_block()
/external/mesa3d/src/gallium/winsys/amdgpu/drm/
Damdgpu_cs.c740 ib->base.current.cdw = 0; in amdgpu_get_new_ib()
770 *ib->ptr_ib_size = ib->base.current.cdw | in amdgpu_set_ib_size()
773 *ib->ptr_ib_size = ib->base.current.cdw; in amdgpu_set_ib_size()
780 ib->used_ib_space += ib->base.current.cdw * 4; in amdgpu_ib_finalize()
782 ib->max_ib_size = MAX2(ib->max_ib_size, ib->base.prev_dw + ib->base.current.cdw); in amdgpu_ib_finalize()
929 unsigned requested_size = rcs->prev_dw + rcs->current.cdw + dw; in amdgpu_cs_check_space()
933 assert(rcs->current.cdw <= rcs->current.max_dw); in amdgpu_cs_check_space()
940 if (rcs->current.max_dw - rcs->current.cdw >= dw) in amdgpu_cs_check_space()
972 while ((rcs->current.cdw & 7) != 4) in amdgpu_cs_check_space()
979 new_ptr_ib_size = &rcs->current.buf[rcs->current.cdw++]; in amdgpu_cs_check_space()
[all …]
/external/mesa3d/src/gallium/winsys/radeon/drm/
Dradeon_drm_cs.c416 assert(cs->base.current.cdw == 0); in radeon_drm_cs_validate()
417 if (cs->base.current.cdw != 0) { in radeon_drm_cs_validate()
427 assert(rcs->current.cdw <= rcs->current.max_dw); in radeon_drm_cs_check_space()
428 return rcs->current.max_dw - rcs->current.cdw >= dw; in radeon_drm_cs_check_space()
554 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
557 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
566 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
569 while (rcs->current.cdw & 7) in radeon_drm_cs_flush()
574 while (rcs->current.cdw & 15) in radeon_drm_cs_flush()
581 if (rcs->current.cdw > rcs->current.max_dw) { in radeon_drm_cs_flush()
[all …]
/external/mesa3d/src/mesa/drivers/dri/radeon/
Dradeon_common.c461 if (radeon->cmdbuf.cs->cdw && !radeon->hw.all_dirty) { in radeonCountStateEmitSize()
539 if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) in radeonEmitState()
542 if (!radeon->cmdbuf.cs->cdw) { in radeonEmitState()
564 fprintf(stderr, "%s %d\n", __func__, radeon->cmdbuf.cs->cdw); in radeonFlush()
571 if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && is_empty_list(&radeon->dma.reserved)) in radeonFlush()
577 if (radeon->cmdbuf.cs->cdw) in radeonFlush()
642 if (rmesa->cmdbuf.cs->cdw) { in rcommonFlushCmdBufLocked()
681 if ((rmesa->cmdbuf.cs->cdw + dwords + 128) > rmesa->cmdbuf.size in rcommonEnsureCmdBufSpace()
684 assert(rmesa->cmdbuf.cs->cdw); in rcommonEnsureCmdBufSpace()
753 n, rmesa->cmdbuf.cs->cdw, function, line); in rcommonBeginBatch()
Dradeon_tcl.c401 + rmesa->radeon.cmdbuf.cs->cdw; in radeon_run_tcl_render()
421 if (emit_end < rmesa->radeon.cmdbuf.cs->cdw) in radeon_run_tcl_render()
423 " We might overflow command buffer.\n", rmesa->radeon.cmdbuf.cs->cdw - emit_end); in radeon_run_tcl_render()
/external/mesa3d/src/mesa/drivers/dri/r200/
Dradeon_common.c461 if (radeon->cmdbuf.cs->cdw && !radeon->hw.all_dirty) { in radeonCountStateEmitSize()
539 if (radeon->cmdbuf.cs->cdw && !radeon->hw.is_dirty && !radeon->hw.all_dirty) in radeonEmitState()
542 if (!radeon->cmdbuf.cs->cdw) { in radeonEmitState()
564 fprintf(stderr, "%s %d\n", __func__, radeon->cmdbuf.cs->cdw); in radeonFlush()
571 if (!radeon->dma.flush && !radeon->cmdbuf.cs->cdw && is_empty_list(&radeon->dma.reserved)) in radeonFlush()
577 if (radeon->cmdbuf.cs->cdw) in radeonFlush()
642 if (rmesa->cmdbuf.cs->cdw) { in rcommonFlushCmdBufLocked()
681 if ((rmesa->cmdbuf.cs->cdw + dwords + 128) > rmesa->cmdbuf.size in rcommonEnsureCmdBufSpace()
684 assert(rmesa->cmdbuf.cs->cdw); in rcommonEnsureCmdBufSpace()
753 n, rmesa->cmdbuf.cs->cdw, function, line); in rcommonBeginBatch()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_debug.c305 if (begin < chunk->cdw) { in si_parse_current_ib()
307 MIN2(end, chunk->cdw) - begin, in si_parse_current_ib()
312 if (end <= chunk->cdw) in si_parse_current_ib()
315 if (begin < chunk->cdw) in si_parse_current_ib()
319 begin -= MIN2(begin, chunk->cdw); in si_parse_current_ib()
320 end -= chunk->cdw; in si_parse_current_ib()
323 assert(end <= cs->current.cdw); in si_parse_current_ib()
395 unsigned gfx_cur = ctx->b.gfx.cs->prev_dw + ctx->b.gfx.cs->current.cdw; in si_log_cs()
/external/mesa3d/src/gallium/winsys/virgl/vtest/
Dvirgl_vtest_socket.c189 vtest_hdr[VTEST_CMD_LEN] = cbuf->base.cdw; in virgl_vtest_submit_cmd()
193 virgl_block_write(vws->sock_fd, cbuf->buf, cbuf->base.cdw * 4); in virgl_vtest_submit_cmd()

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