| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-csel.ll | 28 ; CHECK: cinv w{{[0-9]+}}, w{{[0-9]+}}, ne
116 ; CHECK: cinv w0, w[[REG]], eq
127 ; CHECK: cinv x0, x[[REG]], eq
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-csel.ll | 28 ; CHECK: cinv w{{[0-9]+}}, w{{[0-9]+}}, ne
117 ; CHECK: cinv w0, w[[REG]], eq
128 ; CHECK: cinv x0, x[[REG]], eq
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | basic-a64-diagnostics.s | 1419 cinv w3, wsp, ne
1420 cinv sp, x9, eq
1421 cinv w8, x7, nv
|
| D | basic-a64-instructions.s | 1425 cinv w3, w5, gt
1426 cinv wzr, w4, le
1427 cinv w9, wzr, lt
1432 cinv x3, x5, gt
1433 cinv xzr, x4, le
1434 cinv x9, xzr, lt
|
| /external/llvm/test/MC/AArch64/ |
| D | basic-a64-diagnostics.s | 1414 cinv w3, wsp, ne
1415 cinv sp, x9, eq
1416 cinv w8, x7, nv
|
| D | basic-a64-instructions.s | 1425 cinv w3, w5, gt
1426 cinv wzr, w4, le
1427 cinv w9, wzr, lt
1432 cinv x3, x5, gt
1433 cinv xzr, x4, le
1434 cinv x9, xzr, lt
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 977 # CHECK: cinv w3, w5, gt
978 # CHECK: cinv wzr, w4, le
980 # CHECK: cinv x3, x5, gt
981 # CHECK: cinv xzr, x4, le
983 # "cinv x1, x0, nv" and "cinv w9, w8, al" are invalid aliases for these two
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | basic-a64-instructions.txt | 978 # CHECK: cinv w3, w5, gt
979 # CHECK: cinv wzr, w4, le
981 # CHECK: cinv x3, x5, gt
982 # CHECK: cinv xzr, x4, le
984 # "cinv x1, x0, nv" and "cinv w9, w8, al" are invalid aliases for these two
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64-inl.h | 360 cinv(rd, rn, cond); in Cinv()
|
| D | assembler-arm64.h | 1504 void cinv(const Register& rd, const Register& rn, Condition cond);
|
| D | assembler-arm64.cc | 1398 void Assembler::cinv(const Register &rd, const Register &rn, Condition cond) { in cinv() function in v8::internal::Assembler
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm-colour | 39 0x~~~~~~~~~~~~~~~~ 5a9612d5 cinv w21, w22, eq
40 0x~~~~~~~~~~~~~~~~ 5a9602d5 cinv w21, w22, ne
41 0x~~~~~~~~~~~~~~~~ da982317 cinv x23, x24, lo
42 0x~~~~~~~~~~~~~~~~ da983317 cinv x23, x24, hs
|
| D | log-disasm | 39 0x~~~~~~~~~~~~~~~~ 5a9612d5 cinv w21, w22, eq
40 0x~~~~~~~~~~~~~~~~ 5a9602d5 cinv w21, w22, ne
41 0x~~~~~~~~~~~~~~~~ da982317 cinv x23, x24, lo
42 0x~~~~~~~~~~~~~~~~ da983317 cinv x23, x24, hs
|
| D | log-cpufeatures-custom | 39 0x~~~~~~~~~~~~~~~~ 5a9612d5 cinv w21, w22, eq
40 0x~~~~~~~~~~~~~~~~ 5a9602d5 cinv w21, w22, ne
41 0x~~~~~~~~~~~~~~~~ da982317 cinv x23, x24, lo
42 0x~~~~~~~~~~~~~~~~ da983317 cinv x23, x24, hs
|
| D | log-cpufeatures | 39 0x~~~~~~~~~~~~~~~~ 5a9612d5 cinv w21, w22, eq
40 0x~~~~~~~~~~~~~~~~ 5a9602d5 cinv w21, w22, ne
41 0x~~~~~~~~~~~~~~~~ da982317 cinv x23, x24, lo
42 0x~~~~~~~~~~~~~~~~ da983317 cinv x23, x24, hs
|
| D | log-cpufeatures-colour | 39 0x~~~~~~~~~~~~~~~~ 5a9612d5 cinv w21, w22, eq
40 0x~~~~~~~~~~~~~~~~ 5a9602d5 cinv w21, w22, ne
41 0x~~~~~~~~~~~~~~~~ da982317 cinv x23, x24, lo
42 0x~~~~~~~~~~~~~~~~ da983317 cinv x23, x24, hs
|
| D | log-all | 149 0x~~~~~~~~~~~~~~~~ 5a9612d5 cinv w21, w22, eq
151 0x~~~~~~~~~~~~~~~~ 5a9602d5 cinv w21, w22, ne
153 0x~~~~~~~~~~~~~~~~ da982317 cinv x23, x24, lo
155 0x~~~~~~~~~~~~~~~~ da983317 cinv x23, x24, hs
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 92 __ cinv(w21, w22, eq); in GenerateTestSequenceBase() local
93 __ cinv(w21, w22, ne); in GenerateTestSequenceBase() local
94 __ cinv(x23, x24, cc); in GenerateTestSequenceBase() local
95 __ cinv(x23, x24, cs); in GenerateTestSequenceBase() local
|
| D | test-disasm-aarch64.cc | 2448 COMPARE(cinv(w1, w2, eq), "cinv w1, w2, eq"); in TEST()
2449 COMPARE(cinv(x3, x4, ne), "cinv x3, x4, ne"); in TEST()
|
| D | test-cpu-features-aarch64.cc | 226 TEST_NONE(cinv_0, cinv(w0, w1, cs))
227 TEST_NONE(cinv_1, cinv(x0, x1, cc))
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 896 void cinv(const Register& rd, const Register& rn, Condition cond);
|
| D | macro-assembler-aarch64.h | 1143 cinv(rd, rn, cond); in Cinv()
|
| D | assembler-aarch64.cc | 757 void Assembler::cinv(const Register& rd, const Register& rn, Condition cond) { in cinv() function in vixl::aarch64::Assembler
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 262 void cinv(const Register& rd, const Register& rn, Condition cond)
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1167 def : InstAlias<"cinv $dst, $src, $cc",
1169 def : InstAlias<"cinv $dst, $src, $cc",
|