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Searched refs:clrbits_le32 (Results 1 – 25 of 224) sorted by relevance

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/external/u-boot/arch/arm/mach-davinci/
Dda850_lowlevel.c40 clrbits_le32(&davinci_syscfg_regs->cfgchip0, PLL_MASTER_LOCK); in da850_pll_init()
46 clrbits_le32(&reg->pllctl, PLLCTL_PLLENSRC); in da850_pll_init()
48 clrbits_le32(&reg->pllctl, PLLCTL_EXTCLKSRC); in da850_pll_init()
51 clrbits_le32(&reg->pllctl, PLLCTL_PLLEN); in da850_pll_init()
66 clrbits_le32(&reg->pllctl, PLLCTL_PLLRST); in da850_pll_init()
76 clrbits_le32(&reg->pllctl, PLLCTL_PLLPWRDN); in da850_pll_init()
79 clrbits_le32(&reg->pllctl, PLLCTL_PLLDIS); in da850_pll_init()
172 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_POWERDWN); in da850_ddr_setup()
173 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_LOCK); in da850_ddr_setup()
175 clrbits_le32(&davinci_syscfg1_regs->vtpio_ctl, VTP_CLKRZ); in da850_ddr_setup()
[all …]
Ddm365_lowlevel.c30 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLPWRDN); in dm365_pll1_init()
32 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_RES_9); in dm365_pll1_init()
40 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLENSRC); in dm365_pll1_init()
43 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLEN); in dm365_pll1_init()
53 clrbits_le32(&dv_pll0_regs->pllctl, PLLCTL_PLLRST); in dm365_pll1_init()
107 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLPWRDN); in dm365_pll2_init()
114 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_RES_9); in dm365_pll2_init()
122 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLENSRC); in dm365_pll2_init()
125 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLEN); in dm365_pll2_init()
135 clrbits_le32(&dv_pll1_regs->pllctl, PLLCTL_PLLRST); in dm365_pll2_init()
[all …]
/external/u-boot/drivers/fpga/
Dsocfpga_arria10.c50 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cfgwdth()
130 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_set_cd_ratio()
224 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_reset()
286 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
289 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_init()
296 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
306 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
308 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00, in fpgamgr_program_init()
324 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01, in fpgamgr_program_init()
391 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02, in fpgamgr_program_poll_usermode()
Dsocfpga_gen5.c59 clrbits_le32(&fpgamgr_regs->ctrl, in fpgamgr_program_init()
75 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK); in fpgamgr_program_init()
96 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK); in fpgamgr_program_init()
148 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK); in fpgamgr_program_poll_cd()
196 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK); in fpgamgr_program_poll_usermode()
/external/u-boot/arch/arm/cpu/arm926ejs/mxs/
Dspl_power_init.c318 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); in mxs_src_power_init()
377 clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); in mxs_enable_4p2_dcdc_input()
381 clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); in mxs_enable_4p2_dcdc_input()
397 clrbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
407 clrbits_le32(&power_regs->hw_power_5vctrl, in mxs_enable_4p2_dcdc_input()
426 clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); in mxs_enable_4p2_dcdc_input()
449 clrbits_le32(&power_regs->hw_power_ctrl, in mxs_enable_4p2_dcdc_input()
476 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); in mxs_power_init_4p2_regulator()
497 clrbits_le32(&power_regs->hw_power_dcdc4p2, in mxs_power_init_4p2_regulator()
548 clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); in mxs_power_init_4p2_regulator()
[all …]
Dspl_mem_init.c259 clrbits_le32(&power_regs->hw_power_vddmemctrl, in mx23_mem_setup_vddmem()
284 clrbits_le32(MXS_DRAM_BASE + 0x20, (1 << 16) | (1 << 8)); in mx23_mem_init()
291 clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17); in mx23_mem_init()
326 clrbits_le32(MXS_DRAM_BASE + 0x40, 1); in mx28_mem_init()
331 clrbits_le32(MXS_DRAM_BASE + 0x44, 1); in mx28_mem_init()
/external/u-boot/drivers/i2c/
Dzynq_i2c.c166 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_probe()
199 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
202 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); in zynq_i2c_read()
210 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
228 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
237 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_read()
258 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_RW); in zynq_i2c_write()
267 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_write()
278 clrbits_le32(&zynq_i2c->control, in zynq_i2c_write()
286 clrbits_le32(&zynq_i2c->control, ZYNQ_I2C_CONTROL_HOLD); in zynq_i2c_write()
/external/u-boot/arch/arm/mach-exynos/
Dpower.c50 clrbits_le32(&power->usbhost_phy_control, in exynos5_set_usbhost_phy_ctrl()
70 clrbits_le32(&power->usbhost_phy_control, in exynos4412_set_usbhost_phy_ctrl()
72 clrbits_le32(&power->hsic1_phy_control, in exynos4412_set_usbhost_phy_ctrl()
74 clrbits_le32(&power->hsic2_phy_control, in exynos4412_set_usbhost_phy_ctrl()
99 clrbits_le32(&power->usbdrd_phy_control, in exynos5_set_usbdrd_phy_ctrl()
117 clrbits_le32(&power->usbdev_phy_control, in exynos5420_set_usbdev_phy_ctrl()
119 clrbits_le32(&power->usbdev1_phy_control, in exynos5420_set_usbdev_phy_ctrl()
Dspl_boot.c74 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in spi_rx_tx()
123 clrbits_le32(&regs->ch_cfg, SPI_CH_CPOL_L); /* CPOL: active high */ in exynos_spi_copy()
126 clrbits_le32(&regs->ch_cfg, SPI_RX_CH_ON | SPI_TX_CH_ON); in exynos_spi_copy()
134 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in exynos_spi_copy()
138 clrbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); /* CS low */ in exynos_spi_copy()
164 clrbits_le32(&regs->mode_cfg, SPI_MODE_CH_WIDTH_WORD | in exynos_spi_copy()
173 clrbits_le32(&regs->ch_cfg, SPI_CH_RST); in exynos_spi_copy()
174 clrbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON); in exynos_spi_copy()
/external/u-boot/drivers/usb/host/
Dehci-exynos.c88 clrbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
105 clrbits_le32(&usb->usbphyctrl0, in exynos5_setup_usb_phy()
114 clrbits_le32(&usb->hsicphyctrl1, hsic_ctrl); in exynos5_setup_usb_phy()
115 clrbits_le32(&usb->hsicphyctrl2, hsic_ctrl); in exynos5_setup_usb_phy()
128 clrbits_le32(&usb->hsicphyctrl1, HSIC_CTRL_PHYSWRST | in exynos5_setup_usb_phy()
131 clrbits_le32(&usb->hsicphyctrl2, HSIC_CTRL_PHYSWRST | in exynos5_setup_usb_phy()
148 clrbits_le32(&usb->usbphyctrl, (PHYPWR_NORMAL_MASK_HSIC0 | in exynos4412_setup_usb_phy()
154 clrbits_le32(&usb->usbphyrstcon, (RSTCON_HOSTPHY_SWRST | RSTCON_SWRST)); in exynos4412_setup_usb_phy()
Dehci-tegra.c320 clrbits_le32(&usbctlr->port_sc1, STS1); in init_phy_mux()
324 clrbits_le32(&usbctlr->port_sc1, STS); in init_phy_mux()
339 clrbits_le32(&usbctlr->hostpc1_devlc, STS); in init_phy_mux()
361 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); in init_utmi_usb_controller()
431 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, in init_utmi_usb_controller()
465 clrbits_le32(&usbctlr->utmip_misc_cfg0, in init_utmi_usb_controller()
494 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); in init_utmi_usb_controller()
527 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
530 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
533 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
[all …]
Dutmi-armada100.c28 clrbits_le32(&phy_regs->utmi_pll, PLL_FBDIV_MASK | PLL_REFDIV_MASK); in utmi_phy_init()
43 clrbits_le32(&phy_regs->utmi_pll, VCOCAL_START); in utmi_phy_init()
48 clrbits_le32(&phy_regs->utmi_tx, RCAL_START); in utmi_phy_init()
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun4i.c75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
79 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
122 clrbits_le32(&dram->ccr, DRAM_CCR_ITM_OFF); in mctl_itm_enable()
142 clrbits_le32(&dram->dllcr[0], DRAM_DLLCR_NRESET | DRAM_DLLCR_DISABLE); in mctl_enable_dll0()
180 clrbits_le32(&dram->dllcr[i], DRAM_DLLCR_NRESET | in mctl_enable_dllx()
295 clrbits_le32(&ccm->gps_clk_cfg, CCM_GPS_CTRL_RESET | CCM_GPS_CTRL_GATE); in mctl_setup_dram_clock()
298 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_GPS); in mctl_setup_dram_clock()
338 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM | CCM_AHB_GATE_DLL); in mctl_setup_dram_clock()
340 clrbits_le32(&ccm->ahb_gate0, CCM_AHB_GATE_SDRAM); in mctl_setup_dram_clock()
390 clrbits_le32(&dram->csr, DRAM_CSR_FAILED); in dramc_scan_readpipe()
[all …]
Ddram_sunxi_dw.c33 clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
371 clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
372 clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
373 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
374 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
375 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
377 clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN); in mctl_sys_init()
380 clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST); in mctl_sys_init()
433 clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f); in mctl_channel_init()
469 clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12)); in mctl_channel_init()
[all …]
Ddram_sun8i_a83t.c277 clrbits_le32(&mctl_ctl->pgcr0, 0x3f << 0 | 0x1 << 30); in mctl_channel_init()
320 clrbits_le32(&mctl_ctl->pgcr2, (0x3 << 6)); in mctl_channel_init()
321 clrbits_le32(&mctl_ctl->dqsgmr, (0x1 << 8) | (0x7)); in mctl_channel_init()
395 clrbits_le32(&ccm->mbus_clk_cfg, MBUS_CLK_GATE); in mctl_sys_init()
396 clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET); in mctl_sys_init()
397 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
398 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
399 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
401 clrbits_le32(&ccm->dram_clk_cfg, 0x01<<31); in mctl_sys_init()
Ddram_sun9i.c273 clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL); in mctl_sys_init()
275 clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL); in mctl_sys_init()
330 clrbits_le32(&mctl_com->ccr, MCTL_CCR_CH0_CLK_EN | MCTL_CCR_CH1_CLK_EN); in mctl_sys_init()
586 clrbits_le32(&mctl_ctl->dfimisc, MCTL_DFIMISC_DFI_INIT_COMPLETE_EN); in mctl_channel_init()
630 clrbits_le32(&mctl_phy->dsgcr, (3 << 6)); in mctl_channel_init()
707 clrbits_le32(&mctl_phy->dx[lane].gcr[2], 0xffff); in mctl_channel_init()
708 clrbits_le32(&mctl_phy->dx[lane].gcr[3], in mctl_channel_init()
746 clrbits_le32(&mctl_phy->pgcr[0], 0x3f); in mctl_channel_init()
810 clrbits_le32(&mctl_phy->pgcr[3], (1 << 25)); in mctl_channel_init()
817 clrbits_le32(&mctl_ctl->rfshctl3, MCTL_RFSHCTL3_DIS_AUTO_REFRESH); in mctl_channel_init()
[all …]
/external/u-boot/board/kmc/kzm9g/
Dkzm9g.c151 clrbits_le32(&cpg->smstpcr3, (1 << 15)); in s_init()
152 clrbits_le32(&cpg_srcr->srcr3, (1 << 15)); in s_init()
153 clrbits_le32(&cpg->smstpcr2, (1 << 18)); in s_init()
154 clrbits_le32(&cpg_srcr->srcr2, (1 << 18)); in s_init()
166 clrbits_le32(&cpg->smstpcr0, (1 << 1)); in s_init()
168 clrbits_le32(&cpg_srcr->srcr0, (1 << 1)); in s_init()
234 clrbits_le32(&cpg->pllecr, (1 << 3)); in s_init()
272 clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); in board_early_init_f()
273 clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0)); in board_early_init_f()
274 clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1)); in board_early_init_f()
[all …]
/external/u-boot/arch/arm/mach-socfpga/
Dfreeze_controller.c48 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
58 clrbits_le32(ioctrl_reg_offset, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
73 clrbits_le32(&freeze_controller_base->hioctrl, reg_cfg_mask); in sys_mgr_frzctrl_freeze_req()
153 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
196 clrbits_le32(&freeze_controller_base->hioctrl, in sys_mgr_frzctrl_thaw_req()
Dreset_manager_arria10.c138 clrbits_le32(&reset_manager_base->brgmodrst, in socfpga_reset_deassert_noc_ddr_scheduler()
187 clrbits_le32(&reset_manager_base->per0modrst, emacmask); in socfpga_emac_manage_reset()
188 clrbits_le32(&reset_manager_base->per0modrst, eccmask); in socfpga_emac_manage_reset()
221 clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr); in socfpga_reset_deassert_bridges_handoff()
251 clrbits_le32(&reset_manager_base->per1modrst, in socfpga_reset_deassert_osc1wd0()
287 clrbits_le32(reg, 1 << RSTMGR_RESET(reset)); in socfpga_per_reset()
/external/u-boot/drivers/ram/stm32mp1/
Dstm32mp1_ddr.c283 clrbits_le32(&ctl->swctl, DDRCTRL_SWCTL_SW_DONE); in start_sw_done()
340 clrbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_POWERDOWN_EN); in stm32mp1_refresh_disable()
341 clrbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); in stm32mp1_refresh_disable()
350 clrbits_le32(&ctl->rfshctl3, DDRCTRL_RFSHCTL3_DIS_AUTO_REFRESH); in stm32mp1_refresh_restore()
397 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
398 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
402 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
412 clrbits_le32(&priv->ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN); in stm32mp1_ddr_init()
428 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
429 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
[all …]
/external/u-boot/board/solidrun/clearfog/
Dclearfog.c117 clrbits_le32(MVEBU_GPIO1_BASE + 0x0, BIT(9)); in board_init()
118 clrbits_le32(MVEBU_GPIO1_BASE + 0x4, BIT(9)); in board_init()
120 clrbits_le32(MVEBU_GPIO0_BASE + 0x0, BIT(19)); in board_init()
121 clrbits_le32(MVEBU_GPIO0_BASE + 0x4, BIT(19)); in board_init()
/external/u-boot/drivers/ram/rockchip/
Dsdram_rk3188.c128 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
130 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
151 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
161 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
162 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
164 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
168 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
282 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
294 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
388 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
[all …]
Dsdram_rk3288.c127 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); in phy_pctrl_reset()
129 clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); in phy_pctrl_reset()
150 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
160 clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); in phy_dll_bypass_set()
161 clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); in phy_dll_bypass_set()
163 clrbits_le32(&publ->datx8[i].dxdllcr, in phy_dll_bypass_set()
167 clrbits_le32(&publ->pir, PIR_DLLBYP); in phy_dll_bypass_set()
340 clrbits_le32(&publ->pgcr, 0x1f); in phy_cfg()
352 clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); in phy_cfg()
446 clrbits_le32(&publ->datx8[2].dxgcr, 1); in set_bandwidth_ratio()
[all …]
/external/u-boot/drivers/usb/dwc3/
Dsamsung_usb_phy.c21 clrbits_le32(&phy->phy_param0, in exynos5_usb3_phy_init()
40 clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK); in exynos5_usb3_phy_init()
46 clrbits_le32(&phy->phy_test, in exynos5_usb3_phy_init()
/external/u-boot/arch/arm/cpu/armv7/sunxi/
Dpsci.c110 clrbits_le32(pwroff, BIT(cpu)); in sunxi_power_switch()
185 clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); in sunxi_cpu_power_off()
262 clrbits_le32(&cpucfg->gen_ctrl, BIT(cpu)); in psci_cpu_on()
265 clrbits_le32(&cpucfg->dbg_ctrl1, BIT(cpu)); in psci_cpu_on()
297 clrbits_le32(GICD_BASE + GICD_IGROUPRn, BIT(15)); in psci_arch_init()

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