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Searched refs:cs0_row (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/arch/arm/mach-rockchip/
Dsdram_common.c16 u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
31 cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
40 chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); in rockchip_sdram_size()
43 chipsize_mb += chipsize_mb >> (cs0_row - cs1_row); in rockchip_sdram_size()
48 rank, col, bk, cs0_row, bw, row_3_4); in rockchip_sdram_size()
/external/u-boot/arch/arm/mach-rockchip/rk3036/
Dsdram_rk3036.c656 noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | in dram_cfg_rbc()
667 noc_config = (config.cs0_row - 13) << 4 | config.bank << 1 | in dram_cfg_rbc()
676 noc_config = 1 << 6 | (config.cs0_row - 13) << 4 | in dram_cfg_rbc()
684 noc_config = (config.bank << 6) | (config.cs0_row - 13) << 4 | in dram_cfg_rbc()
712 (config.cs0_row - 13) << DDR_CS0_ROW_SHIFT | in sdram_all_config()
721 u32 size, os_reg, cs0_row, cs1_row, col, bank, rank; in sdram_size() local
726 cs0_row = 13 + ((os_reg >> DDR_CS0_ROW_SHIFT) & DDR_CS0_ROW_MASK); in sdram_size()
733 size = 1 << (cs0_row + col + bank + 1); in sdram_size()
736 size += size >> (cs0_row - cs1_row); in sdram_size()
/external/u-boot/board/rockchip/evb_rk3036/
Devb_rk3036.c17 config->cs0_row = 15; in get_ddr_config()
/external/u-boot/board/rockchip/kylin_rk3036/
Dkylin_rk3036.c18 config->cs0_row = 15; in get_ddr_config()
/external/u-boot/drivers/ram/rockchip/
Dsdram_rk322x.c541 if ((config->rank == 2) && (config->cs1_row == config->cs0_row)) { in dram_cfg_rbc()
550 noc_config = ((config->cs0_row - 13) << 4) | ((config->bk - 2) << 2) | in dram_cfg_rbc()
560 noc_config = ((config->bk - 2) << 6) | ((config->cs0_row - 13) << 4) | in dram_cfg_rbc()
590 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(0); in dram_all_config()
670 sdram_params->ch[0].cs0_row = row; in dram_cap_detect()
Dsdram_rk3288.c606 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); in dram_all_config()
717 sdram_params->ch[channel].cs0_row = row; in sdram_col_row_detect()
730 tmp |= ((sdram_params->ch[0].cs0_row - 12) << 4); in sdram_get_niu_config()
750 (sdram_params->ch[0].cs0_row + in sdram_get_stride()
Ddmc-rk3368.c651 params->chan.cs0_row = row; in sdram_col_row_detect()
663 const u8 rows = params->chan.cs0_row; in msch_niu_config()
785 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); in dram_all_config()
Dsdram_rk3188.c549 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); in dram_all_config()
673 sdram_params->ch[channel].cs0_row = row; in sdram_col_row_detect()
684 row = sdram_params->ch[0].cs0_row; in sdram_get_niu_config()
Dsdram_rk3399.c914 cs0_cap = (1 << (sdram_params->ch[channel].cs0_row in set_ddrconfig()
919 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row in set_ddrconfig()
956 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel); in dram_all_config()
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dsdram_rk3399.h89 unsigned int cs0_row; member
Dsdram.h29 u8 cs0_row; member
Dsdram_rk3036.h321 u32 cs0_row; member
Dsdram_rk322x.h29 u8 cs0_row; member
/external/u-boot/doc/device-tree-bindings/clock/
Drockchip,rk3288-dmc.txt101 cs0_row