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Searched refs:ddr_width (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_init.c359 __maybe_unused u32 ddr_width = BUS_WIDTH; in ddr3_init_main() local
489 ddr_width = 32; in ddr3_init_main()
497 ddr_width = 32; in ddr3_init_main()
499 ddr_width = 16; in ddr3_init_main()
504 status = ddr3_dunit_setup(ecc, hclk_time_ps, &ddr_width); in ddr3_init_main()
538 if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) & in ddr3_init_main()
605 status = ddr3_hw_training(target_freq, ddr_width, in ddr3_init_main()
628 status = ddr3_hw_training(target_freq, ddr_width, in ddr3_init_main()
Dddr3_init.h95 int ddr3_hw_training(u32 target_freq, u32 ddr_width,
117 int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width);
Dddr3_sdram.c298 switch (dram_info->ddr_width) { in ddr3_sdram_pbs_compare()
348 if (dram_info->ddr_width > 16) { in ddr3_sdram_pbs_compare()
473 if (dram_info->ddr_width > 16) { in ddr3_sdram_direct_compare()
625 if (dram_info->ddr_width > 16) { in ddr3_sdram_dqs_compare()
Dddr3_hw_training.c77 int ddr3_hw_training(u32 target_freq, u32 ddr_width, int xor_bypass, in ddr3_hw_training() argument
96 dram_info.ddr_width = ddr_width; in ddr3_hw_training()
97 dram_info.num_of_std_pups = ddr_width / PUP_SIZE; in ddr3_hw_training()
120 dram_info.num_of_total_pups = ddr_width / PUP_SIZE + dram_info.ecc_ena; in ddr3_hw_training()
Dddr3_spd.c574 int ddr3_dunit_setup(u32 ecc_ena, u32 hclk_time, u32 *ddr_width) argument
598 status = ddr3_spd_init(&dimm_info[0], 0, *ddr_width);
627 *ddr_width);
739 if (*ddr_width == 64) {
751 if (*ddr_width == 32) {
Dddr3_write_leveling.c188 u32 ddr_width, tmp_pup, idx; in ddr3_wl_supplement() local
193 ddr_width = dram_info->ddr_width; in ddr3_wl_supplement()
198 switch (ddr_width) { in ddr3_wl_supplement()
Dddr3_pbs.c416 switch (dram_info->ddr_width) { in ddr3_tx_shift_dqs_adll_step_before_fail()
927 switch (dram_info->ddr_width) { in ddr3_rx_shift_dqs_to_first_fail()
1537 switch (dram_info->ddr_width) { in ddr3_load_pbs_patterns()
Dddr3_hw_training.h257 u32 ddr_width; /* 32/64 Bit or 16/32 Bit */ member
Dddr3_dqs.c97 switch (dram_info->ddr_width) { in ddr3_dqs_choose_pattern()