Searched refs:ddr_wrlvl_cntl_3 (Results 1 – 10 of 10) sorted by relevance
119 if (regs->ddr_wrlvl_cntl_3) in fsl_ddr_set_memctl_regs()120 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); in fsl_ddr_set_memctl_regs()
142 if (regs->ddr_wrlvl_cntl_3) in fsl_ddr_set_memctl_regs()143 out_be32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); in fsl_ddr_set_memctl_regs()
204 if (regs->ddr_wrlvl_cntl_3) in fsl_ddr_set_memctl_regs()205 ddr_out32(&ddr->ddr_wrlvl_cntl_3, regs->ddr_wrlvl_cntl_3); in fsl_ddr_set_memctl_regs()
2295 ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3; in set_ddr_wrlvl_cntl()2296 debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3); in set_ddr_wrlvl_cntl()
669 CFG_REGS(ddr_wrlvl_cntl_3), in print_fsl_memctl_config_regs()760 CFG_REGS(ddr_wrlvl_cntl_3), in fsl_ddr_regs_edit()
96 .ddr_wrlvl_cntl_3 = 0,
75 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); in ddrmc_init()
62 u32 ddr_wrlvl_cntl_3; /* write leveling control 3 */ member
286 unsigned int ddr_wrlvl_cntl_3; member
181 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3); in ddrmc_init()