Searched refs:def_instr_begin (Results 1 – 15 of 15) sorted by relevance
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 218 MRI->def_instr_begin(OrigSrc0); in isProfitableToTransform()
231 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform()
311 MRI->def_instr_begin(OrigSrc0); in transformInstruction()
330 MRI->def_instr_begin(OrigSrc1); in transformInstruction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64AdvSIMDScalarPass.cpp | 211 MRI->def_instr_begin(OrigSrc0); in isProfitableToTransform()
224 MRI->def_instr_begin(OrigSrc1); in isProfitableToTransform()
304 MRI->def_instr_begin(OrigSrc0); in transformInstruction()
323 MRI->def_instr_begin(OrigSrc1); in transformInstruction()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 52 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), in isImplicitlyDef()
339 It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end(); in runOnMachineFunction()
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| D | SIMachineScheduler.cpp | 293 UI = MRI->def_instr_begin(Reg), in isDefBetween()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600OptimizeVectorRegisters.cpp | 62 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg), in isImplicitlyDef()
361 It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end(); in runOnMachineFunction()
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| D | SIMachineScheduler.cpp | 314 UI = MRI->def_instr_begin(Reg), in isDefBetween()
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 337 def_instr_iterator I = def_instr_begin(Reg); in getVRegDef()
348 def_instr_iterator I = def_instr_begin(Reg); in getUniqueVRegDef()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | InstructionSelect.cpp | 189 MI = &*MRI.def_instr_begin(VReg); in runOnMachineFunction()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | LiveRangeShrink.cpp | 199 MachineInstr &DefInstr = *MRI.def_instr_begin(Reg); in runOnMachineFunction()
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| D | MachineRegisterInfo.cpp | 404 def_instr_iterator I = def_instr_begin(Reg); in getVRegDef()
415 def_instr_iterator I = def_instr_begin(Reg); in getUniqueVRegDef()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 363 def_instr_iterator def_instr_begin(unsigned RegNo) const { in def_instr_begin() function
372 return make_range(def_instr_begin(Reg), def_instr_end()); in def_instructions()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 398 def_instr_iterator def_instr_begin(unsigned RegNo) const { in def_instr_begin() function
407 return make_range(def_instr_begin(Reg), def_instr_end()); in def_instructions()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 456 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), in regIsPICBase()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.cpp | 2300 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg), in regIsPICBase()
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| D | X86ISelLowering.cpp | 24190 MachineInstr &AddendDef = *MRI.def_instr_begin(AddendOp.getReg()); in emitFMA3Instr()
24209 MachineInstr &PHISrcInst = *MRI.def_instr_begin(PHISrcOp.getReg()); in emitFMA3Instr()
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