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Searched refs:def_instr_end (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp219 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
232 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
312 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
331 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64AdvSIMDScalarPass.cpp212 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
225 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in isProfitableToTransform()
305 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
324 assert(std::next(Def) == MRI->def_instr_end() && "Multiple def in SSA!"); in transformInstruction()
/external/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp53 E = MRI.def_instr_end(); It != E; ++It) { in isImplicitlyDef()
339 It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end(); in runOnMachineFunction()
DSIMachineScheduler.cpp294 UE = MRI->def_instr_end(); UI != UE; ++UI) { in isDefBetween()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp63 E = MRI.def_instr_end(); It != E; ++It) { in isImplicitlyDef()
361 It = MRI->def_instr_begin(Reg), E = MRI->def_instr_end(); in runOnMachineFunction()
DSIMachineScheduler.cpp315 UE = MRI->def_instr_end(); UI != UE; ++UI) { in isDefBetween()
/external/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp338 assert((I.atEnd() || std::next(I) == def_instr_end()) && in getVRegDef()
349 if (std::next(I) != def_instr_end()) in getUniqueVRegDef()
/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h366 static def_instr_iterator def_instr_end() { in def_instr_end() function
372 return make_range(def_instr_begin(Reg), def_instr_end()); in def_instructions()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineRegisterInfo.cpp405 assert((I.atEnd() || std::next(I) == def_instr_end()) && in getVRegDef()
416 if (std::next(I) != def_instr_end()) in getUniqueVRegDef()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h401 static def_instr_iterator def_instr_end() { in def_instr_end() function
407 return make_range(def_instr_begin(Reg), def_instr_end()); in def_instructions()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrInfo.cpp457 E = MRI.def_instr_end(); I != E; ++I) { in regIsPICBase()
/external/llvm/lib/Target/X86/
DX86InstrInfo.cpp2301 E = MRI.def_instr_end(); I != E; ++I) { in regIsPICBase()