Searched refs:div_fsys1 (Results 1 – 6 of 6) sorted by relevance
408 div = sub_div = readl(&clk->div_fsys1); in exynos5_get_periph_rate()502 div = readl(&clk->div_fsys1); in exynos542x_get_periph_rate()806 ratio = readl(&clk->div_fsys1); in exynos4_get_mmc_clk()807 pre_ratio = readl(&clk->div_fsys1); in exynos4_get_mmc_clk()848 addr = (unsigned int)&clk->div_fsys1; in exynos4_set_mmc_clk()881 addr = (unsigned int)&clk->div_fsys1; in exynos5_set_mmc_clk()905 addr = (unsigned int)&clk->div_fsys1; in exynos5420_set_mmc_clk()
69 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in system_clock_init()
942 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1); in exynos5420_system_clock_init()999 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; in emmc_boot_clk_div_set()1001 writel(div_mmc, (unsigned int) &clk->div_fsys1); in emmc_boot_clk_div_set()
95 unsigned int div_fsys1; member332 unsigned int div_fsys1; member723 unsigned int div_fsys1; member1131 unsigned int div_fsys1; member
315 clrsetbits_le32(&clk->div_fsys1, clr, set); in board_clock_init()
329 writel(CLK_DIV_FSYS1_VAL, (unsigned int)&clk->div_fsys1); in board_clock_init()