| /external/capstone/suite/MC/PowerPC/ |
| D | ppc64-encoding.s.cs | 104 0x7c,0x43,0x23,0x96 = divwu 2, 3, 4
105 0x7c,0x43,0x23,0x97 = divwu. 2, 3, 4
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| /external/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding.s | 430 # CHECK-BE: divwu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x96]
431 # CHECK-LE: divwu 2, 3, 4 # encoding: [0x96,0x23,0x43,0x7c]
432 divwu 2, 3, 4
433 # CHECK-BE: divwu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x97]
434 # CHECK-LE: divwu. 2, 3, 4 # encoding: [0x97,0x23,0x43,0x7c]
435 divwu. 2, 3, 4
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/PowerPC/ |
| D | ppc64-encoding.s | 503 # CHECK-BE: divwu 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x96]
504 # CHECK-LE: divwu 2, 3, 4 # encoding: [0x96,0x23,0x43,0x7c]
505 divwu 2, 3, 4
506 # CHECK-BE: divwu. 2, 3, 4 # encoding: [0x7c,0x43,0x23,0x97]
507 # CHECK-LE: divwu. 2, 3, 4 # encoding: [0x97,0x23,0x43,0x7c]
508 divwu. 2, 3, 4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64le-encoding.txt | 334 # CHECK: divwu 2, 3, 4
337 # CHECK: divwu. 2, 3, 4
|
| D | ppc64-encoding.txt | 358 # CHECK: divwu 2, 3, 4
361 # CHECK: divwu. 2, 3, 4
|
| /external/llvm/test/MC/Disassembler/PowerPC/ |
| D | ppc64-encoding.txt | 337 # CHECK: divwu 2, 3, 4
340 # CHECK: divwu. 2, 3, 4
|
| D | ppc64le-encoding.txt | 334 # CHECK: divwu 2, 3, 4
337 # CHECK: divwu. 2, 3, 4
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCSchedule.td | 158 // divwu IntDivW
|
| D | PPCInstrInfo.td | 1174 "divwu $rT, $rA, $rB", IntDivW,
|
| /external/v8/src/compiler/ppc/ |
| D | code-generator-ppc.cc | 1492 __ divwu(i.OutputRegister(), i.InputRegister(0), i.InputRegister(1)); in AssembleArchInstruction() local
1524 ASSEMBLE_MODULO(divwu, mullw); in AssembleArchInstruction()
|
| /external/v8/src/ppc/ |
| D | assembler-ppc.h | 1052 void divwu(Register dst, Register src1, Register src2, OEBit o = LeaveOE,
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| D | constants-ppc.h | 2016 V(divwu, DIVWU, 0x7C000396) \
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| D | assembler-ppc.cc | 910 void Assembler::divwu(Register dst, Register src1, Register src2, OEBit o, in divwu() function in v8::internal::Assembler
|
| /external/u-boot/doc/ |
| D | README.POST | 452 subfc, subfe, subme, subze, mullw, mulhw, mulhwu, divw, divwu,
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 2461 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 2741 "divwu", "$rT, $rA, $rB", IIC_IntDivW,
|