| /external/u-boot/arch/arm/mach-sunxi/ |
| D | dram_sun4i.c | 60 struct sunxi_dram_reg *dram = in mctl_ddr3_reset() local
73 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
79 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
81 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
100 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; in mctl_set_drive() local
103 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), in mctl_set_drive()
105 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), in mctl_set_drive()
113 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; in mctl_itm_disable() local
115 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); in mctl_itm_disable()
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| D | Kconfig | 12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
365 int "sunxi dram type"
369 Set the dram type, 3: DDR3, 7: LPDDR3
372 int "sunxi dram clock speed"
380 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
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| /external/u-boot/arch/arm/cpu/arm926ejs/lpc32xx/ |
| D | dram.c | 27 void ddr_init(struct emc_dram_settings *dram) in ddr_init() argument
39 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init()
40 writel(dram->config0, &emc->config0); in ddr_init()
41 writel(dram->rascas0, &emc->rascas0); in ddr_init()
42 writel(dram->rdconfig, &emc->read_config); in ddr_init()
44 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
45 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
46 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); in ddr_init()
47 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); in ddr_init()
48 writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); in ddr_init()
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| D | Makefile | 8 obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
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| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_rk322x.c | 363 static void phy_softreset(struct dram_info *dram) in phy_softreset() argument
365 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in phy_softreset()
366 struct rk322x_grf *grf = dram->grf; in phy_softreset()
378 static void set_bw(struct dram_info *dram, u32 bw) in set_bw() argument
380 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; in set_bw()
381 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in set_bw()
382 struct rk322x_grf *grf = dram->grf; in set_bw()
577 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
595 writel(sys_reg, &dram->grf->os_reg[2]); in dram_all_config()
600 static int dram_cap_detect(struct dram_info *dram, in dram_cap_detect() argument
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| D | sdram_rk3188.c | 532 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
554 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
557 ddr_rank_2_row15en(dram->grf, 0); in dram_all_config()
559 ddr_rank_2_row15en(dram->grf, 1); in dram_all_config()
561 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
564 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect() argument
569 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
572 ddr_rank_2_row15en(dram->grf, 0); in sdram_rank_bw_detect()
595 dram->grf); in sdram_rank_bw_detect()
605 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
[all …]
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| D | sdram_rk3288.c | 589 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
611 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
613 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
614 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); in dram_all_config()
617 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect() argument
622 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
648 dram->grf); in sdram_rank_bw_detect()
658 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
660 ddr_phy_ctl_reset(dram->cru, channel, 0); in sdram_rank_bw_detect()
670 static int sdram_col_row_detect(struct dram_info *dram, int channel, in sdram_col_row_detect() argument
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| D | sdram_rk3399.c | 931 static void dram_all_config(struct dram_info *dram, in dram_all_config() argument
961 ddr_msch_regs = dram->chan[channel].msch; in dram_all_config()
976 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], in dram_all_config()
980 writel(sys_reg, &dram->pmugrf->os_reg2); in dram_all_config()
981 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, in dram_all_config()
987 &dram->pmucru->pmucru_rstnhold_con[1]); in dram_all_config()
988 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); in dram_all_config()
991 static int switch_to_phy_index1(struct dram_info *dram, in switch_to_phy_index1() argument
1002 &dram->cic->cic_ctrl0); in switch_to_phy_index1()
1003 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { in switch_to_phy_index1()
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| /external/u-boot/arch/arm/mach-mvebu/ |
| D | cpu.c | 513 const struct mbus_dram_target_info *dram; in ahci_mvebu_mbus_config() local
516 dram = mvebu_mbus_dram_info(); in ahci_mvebu_mbus_config()
524 for (i = 0; i < dram->num_cs; i++) { in ahci_mvebu_mbus_config()
525 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config()
528 (dram->mbus_dram_target_id << 4) | 1, in ahci_mvebu_mbus_config()
562 const struct mbus_dram_target_info *dram) in xhci_mvebu_mbus_config() argument
571 for (i = 0; i < dram->num_cs; i++) { in xhci_mvebu_mbus_config()
572 const struct mbus_dram_window *cs = dram->cs + i; in xhci_mvebu_mbus_config()
576 (dram->mbus_dram_target_id << 4) | 1, in xhci_mvebu_mbus_config()
586 const struct mbus_dram_target_info *dram; in board_xhci_enable() local
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| D | Makefile | 15 obj-y = dram.o
22 obj-y += dram.o
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| /external/u-boot/arch/x86/dts/ |
| D | galileo.dts | 50 dram-width = <DRAM_WIDTH_X8>;
51 dram-speed = <DRAM_FREQ_800>;
52 dram-type = <DRAM_TYPE_DDR3>;
62 dram-density = <DRAM_DENSITY_1G>;
63 dram-cl = <6>;
64 dram-ras = <0x0000927c>;
65 dram-wtr = <0x00002710>;
66 dram-rrd = <0x00002710>;
67 dram-faw = <0x00009c40>;
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| /external/u-boot/arch/arm/mach-uniphier/clk/ |
| D | Makefile | 5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
6 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
10 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
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| /external/u-boot/drivers/mmc/ |
| D | mv_sdhci.c | 16 const struct mbus_dram_target_info *dram; in sdhci_mvebu_mbus_config() local
19 dram = mvebu_mbus_dram_info(); in sdhci_mvebu_mbus_config()
26 for (i = 0; i < dram->num_cs; i++) { in sdhci_mvebu_mbus_config()
27 const struct mbus_dram_window *cs = dram->cs + i; in sdhci_mvebu_mbus_config()
31 (dram->mbus_dram_target_id << 4) | 1, in sdhci_mvebu_mbus_config()
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| /external/u-boot/drivers/ata/ |
| D | mvsata_ide.c | 107 const struct mbus_dram_target_info *dram; in mvsata_ide_conf_mbus_windows() local
110 dram = mvebu_mbus_dram_info(); in mvsata_ide_conf_mbus_windows()
118 for (i = 0; i < dram->num_cs; i++) { in mvsata_ide_conf_mbus_windows()
119 const struct mbus_dram_window *cs = dram->cs + i; in mvsata_ide_conf_mbus_windows()
121 (dram->mbus_dram_target_id << 4) | 1, in mvsata_ide_conf_mbus_windows()
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| /external/u-boot/drivers/usb/host/ |
| D | ehci-marvell.c | 55 const struct mbus_dram_target_info *dram; in usb_brg_adrdec_setup() local
58 dram = mvebu_mbus_dram_info(); in usb_brg_adrdec_setup()
65 for (i = 0; i < dram->num_cs; i++) { in usb_brg_adrdec_setup()
66 const struct mbus_dram_window *cs = dram->cs + i; in usb_brg_adrdec_setup()
70 (dram->mbus_dram_target_id << 4) | 1, in usb_brg_adrdec_setup()
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| /external/u-boot/drivers/video/ |
| D | mvebu_lcd.c | 78 const struct mbus_dram_target_info *dram; in mvebu_lcd_conf_mbus_registers() local
81 dram = mvebu_mbus_dram_info(); in mvebu_lcd_conf_mbus_registers()
91 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
92 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()
94 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()
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| /external/u-boot/drivers/pci/ |
| D | pci_mvebu.c | 286 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info(); in mvebu_pcie_setup_wins() local
309 for (i = 0; i < dram->num_cs; i++) { in mvebu_pcie_setup_wins()
310 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_pcie_setup_wins()
317 (dram->mbus_dram_target_id << 4) | 1, in mvebu_pcie_setup_wins()
328 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1)); in mvebu_pcie_setup_wins()
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| /external/u-boot/doc/device-tree-bindings/misc/ |
| D | intel,baytrail-fsp.txt | 75 - fsp,dram-speed
76 - fsp,dram-type
137 fsp,dram-speed = <DRAM_SPEED_1066MTS>;
138 fsp,dram-type = <DRAM_TYPE_DDR3L>;
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| /external/u-boot/arch/mips/mach-bmips/ |
| D | Makefile | 3 obj-y += dram.o
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| /external/u-boot/arch/arm/cpu/arm926ejs/armada100/ |
| D | Makefile | 7 obj-y = cpu.o timer.o dram.o
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| /external/u-boot/arch/arm/dts/ |
| D | sunxi-libretech-all-h3-cc.dtsi | 72 reg_vcc_dram: vcc-dram {
74 regulator-name = "vcc-dram";
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| /external/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| D | sys_proto.h | 20 void ddr_init(const struct emc_dram_settings *dram);
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| /external/u-boot/arch/mips/mach-ath79/ |
| D | Makefile | 5 obj-y += dram.o
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| /external/u-boot/arch/x86/cpu/qemu/ |
| D | Makefile | 8 obj-y += dram.o
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| /external/u-boot/arch/x86/cpu/quark/ |
| D | Makefile | 5 obj-y += car.o dram.o msg_port.o quark.o
|