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Searched refs:epll_con0 (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dclock.c199 r = readl(&clk->epll_con0); in exynos4_get_pll_clk()
229 r = readl(&clk->epll_con0); in exynos4x12_get_pll_clk()
260 r = readl(&clk->epll_con0); in exynos5_get_pll_clk()
318 r = readl(&clk->epll_con0); in exynos542x_get_pll_clk()
1275 epll_con = readl(&clk->epll_con0); in exynos5_set_epll_clk()
1305 writel(epll_con, &clk->epll_con0); in exynos5_set_epll_clk()
1310 while (!(readl(&clk->epll_con0) & in exynos5_set_epll_clk()
Dclock_init_exynos4.c89 writel(EPLL_CON0_VAL, &clk->epll_con0); in system_clock_init()
Dclock_init_exynos5.c657 writel(val, &clk->epll_con0); in exynos5250_system_clock_init()
658 while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0) in exynos5250_system_clock_init()
864 writel(val, &clk->epll_con0); in exynos5420_system_clock_init()
865 while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0) in exynos5420_system_clock_init()
/external/u-boot/arch/arm/mach-exynos/include/mach/
Dclock.h43 unsigned int epll_con0; member
275 unsigned int epll_con0; member
663 unsigned int epll_con0; member
1050 unsigned int epll_con0; member
/external/u-boot/board/samsung/trats/
Dtrats.c344 writel(EPLL_CON0_VAL, (unsigned int)&clk->epll_con0); in board_clock_init()