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Searched refs:fcvtl (Results 1 – 25 of 49) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dfp16-v4-instructions.ll7 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
8 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
32 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
33 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
48 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
49 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
64 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
65 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
120 ; CHECK-COMMON: fcvtl v0.4s, v0.4h
257 ; CHECK-COMMON-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
[all …]
Dcomplex-fp-to-int.ll5 ; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
14 ; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
Dvector-fcopysign.ll127 ; CHECK-NEXT: fcvtl v1.2d, v1.2s
154 ; CHECK-NEXT: fcvtl v2.2d, v2.2s
Darm64-vcvt_f32_su32.ll38 ; CHECK: fcvtl v0.4s, v0.4h
Dfp16-v8-instructions.ll239 ; CHECK: fcvtl v0.4s, v0.4h
396 ; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
410 ; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
423 ; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
437 ; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
Darm64-vcvt_f.ll7 ; CHECK: fcvtl v0.2d, v0.2s
Dfcvt_combine.ll60 ; CHECK: fcvtl v0.2d, v0.2s
/external/llvm/test/CodeGen/AArch64/
Dfp16-v4-instructions.ll6 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
7 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
27 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
28 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
39 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
40 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
51 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
52 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
100 ; CHECK: fcvtl v0.4s, v0.4h
231 ; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
[all …]
Dcomplex-fp-to-int.ll5 ; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
14 ; CHECK: fcvtl [[VAL64:v[0-9]+]].2d, v0.2s
Dfp16-v8-instructions.ll218 ; CHECK: fcvtl v0.4s, v0.4h
372 ; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
386 ; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
399 ; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
413 ; CHECK-DAG: fcvtl [[LO:v[0-9]+\.4s]], v0.4h
Dvector-fcopysign.ll127 ; CHECK-NEXT: fcvtl v1.2d, v1.2s
154 ; CHECK-NEXT: fcvtl v2.2d, v2.2s
Darm64-vcvt_f32_su32.ll38 ; CHECK: fcvtl v0.4s, v0.4h
Darm64-vcvt_f.ll7 ; CHECK: fcvtl v0.2d, v0.2s
Dfcvt_combine.ll60 ; CHECK: fcvtl v0.2d, v0.2s
/external/capstone/suite/MC/AArch64/
Dneon-simd-misc.s.cs140 0x29,0x78,0x21,0x0e = fcvtl v9.4s, v1.4h
141 0x20,0x78,0x61,0x0e = fcvtl v0.2d, v1.2s
/external/llvm/test/MC/AArch64/
Dneon-simd-misc.s447 fcvtl v9.4s, v1.4h
448 fcvtl v0.2d, v1.2s
Darm64-advsimd.s804 fcvtl v1.4s, v5.4h
805 fcvtl v2.2d, v6.2s
809 ; CHECK: fcvtl v1.4s, v5.4h ; encoding: [0xa1,0x78,0x21,0x0e]
810 ; CHECK: fcvtl v2.2d, v6.2s ; encoding: [0xc2,0x78,0x61,0x0e]
Dneon-diagnostics.s5836 fcvtl v12.4s, v4.8h
5837 fcvtl v17.2d, v28.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-simd-misc.s447 fcvtl v9.4s, v1.4h
448 fcvtl v0.2d, v1.2s
Darm64-advsimd.s804 fcvtl v1.4s, v5.4h
805 fcvtl v2.2d, v6.2s
809 ; CHECK: fcvtl v1.4s, v5.4h ; encoding: [0xa1,0x78,0x21,0x0e]
810 ; CHECK: fcvtl v2.2d, v6.2s ; encoding: [0xc2,0x78,0x61,0x0e]
Dneon-diagnostics.s5776 fcvtl v12.4s, v4.8h
5777 fcvtl v17.2d, v28.4s
/external/v8/src/arm64/
Dmacro-assembler-arm64.h1314 fcvtl(vd, vn); in Fcvtl()
Dsimulator-arm64.h1975 LogicVRegister fcvtl(VectorFormat vform, LogicVRegister dst,
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt555 # CHECK: fcvtl v0.4s, v0.4h
557 # CHECK: fcvtl v0.2d, v0.2s
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-advsimd.txt555 # CHECK: fcvtl v0.4s, v0.4h
557 # CHECK: fcvtl v0.2d, v0.2s

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