/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
D | fminnm.s | 10 fminnm z0.h, p0/m, z0.h, #0.000000000000000 label 16 fminnm z0.h, p0/m, z0.h, #0.0 label 22 fminnm z0.s, p0/m, z0.s, #0.0 label 28 fminnm z0.d, p0/m, z0.d, #0.0 label 34 fminnm z31.h, p7/m, z31.h, #1.000000000000000 label 40 fminnm z31.h, p7/m, z31.h, #1.0 label 46 fminnm z31.s, p7/m, z31.s, #1.0 label 52 fminnm z31.d, p7/m, z31.d, #1.0 label 58 fminnm z0.h, p7/m, z0.h, z31.h label 64 fminnm z0.s, p7/m, z0.s, z31.s label [all …]
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D | fminnm-diagnostics.s | 6 fminnm z0.h, p0/m, z0.h, #0.5 label 11 fminnm z0.h, p0/m, z0.h, #-0.0 label 16 fminnm z0.h, p0/m, z0.h, #0.0000000000000000000000001 label 21 fminnm z0.h, p0/m, z0.h, #1.0000000000000000000000001 label 26 fminnm z0.h, p0/m, z0.h, #0.9999999999999999999999999 label 35 fminnm z0.h, p7/m, z1.h, z31.h label 44 fminnm z0.b, p7/m, z0.b, z31.b label 49 fminnm z0.h, p7/m, z0.h, z31.s label 58 fminnm z0.h, p8/m, z0.h, z31.h label
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/external/llvm/test/MC/AArch64/ |
D | directive-arch-negative.s | 10 fminnm d0, d0, d1 define 13 # CHECK: fminnm d0, d0, d1 20 fminnm d0, d0, d1 define 23 # CHECK: fminnm d0, d0, d1 30 fminnm d0, d0, d1 define 33 # CHECK: fminnm d0, d0, d1
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D | neon-max-min.s | 115 fminnm v10.4h, v15.4h, v22.4h 116 fminnm v10.8h, v15.8h, v22.8h 117 fminnm v10.2s, v15.2s, v22.2s 118 fminnm v3.4s, v5.4s, v6.4s 119 fminnm v17.2d, v13.2d, v2.2d
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D | directive-cpu.s | 5 fminnm d0, d0, d1 define 9 fminnm d0, d0, d1 define 13 fminnm d0, d0, d1 define
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D | arm64-fp-encoding.s | 71 fminnm h1, h2, h3 72 fminnm s1, s2, s3 73 fminnm d1, d2, d3 define 80 ; FP16: fminnm h1, h2, h3 ; encoding: [0x41,0x78,0xe3,0x1e] 82 ; NO-FP16-NEXT: fminnm h1, h2, h3 83 ; CHECK: fminnm s1, s2, s3 ; encoding: [0x41,0x78,0x23,0x1e] 84 ; CHECK: fminnm d1, d2, d3 ; encoding: [0x41,0x78,0x63,0x1e]
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D | fullfp16-neon-neg.s | 204 fminnm v10.4h, v15.4h, v22.4h 206 fminnm v10.8h, v15.8h, v22.8h
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D | arm64-advsimd.s | 322 fminnm.2s v0, v0, v0 392 ; CHECK: fminnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0xa0,0x0e] 457 fminnm.4h v0, v0, v0 482 ; CHECK: fminnm.4h v0, v0, v0 ; encoding: [0x00,0x04,0xc0,0x0e] 507 fminnm.8h v0, v0, v0 532 ; CHECK: fminnm.8h v0, v0, v0 ; encoding: [0x00,0x04,0xc0,0x4e]
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/external/llvm/test/CodeGen/AArch64/ |
D | arm64-vminmaxnm.ll | 25 ; CHECK: fminnm.2s v0, v0, v1 27 …%vminnm2.i = tail call <2 x float> @llvm.aarch64.neon.fminnm.v2f32(<2 x float> %a, <2 x float> %b)… 32 ; CHECK: fminnm.4s v0, v0, v1 34 …%vminnm2.i = tail call <4 x float> @llvm.aarch64.neon.fminnm.v4f32(<4 x float> %a, <4 x float> %b)… 39 ; CHECK: fminnm.2d v0, v0, v1 41 …%vminnm2.i = tail call <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double> %a, <2 x double> … 53 ; CHECK: fminnm d0, d0, d1 55 %vmaxnm2.i = tail call double @llvm.aarch64.neon.fminnm.f64(double %a, double %b) nounwind 59 declare <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double>, <2 x double>) nounwind readnone 60 declare <4 x float> @llvm.aarch64.neon.fminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone [all …]
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D | arm64-fmax-safe.ll | 24 ; must become fminnm, not fmin. 32 ; CHECK: fminnm s
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D | arm64-neon-add-sub.ll | 212 ; CHECK: fminnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 213 %1 = tail call <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double> %a, <1 x double> %b) 232 declare <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double>, <1 x double>)
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | arm64-vminmaxnm.ll | 25 ; CHECK: fminnm.2s v0, v0, v1 27 …%vminnm2.i = tail call <2 x float> @llvm.aarch64.neon.fminnm.v2f32(<2 x float> %a, <2 x float> %b)… 32 ; CHECK: fminnm.4s v0, v0, v1 34 …%vminnm2.i = tail call <4 x float> @llvm.aarch64.neon.fminnm.v4f32(<4 x float> %a, <4 x float> %b)… 39 ; CHECK: fminnm.2d v0, v0, v1 41 …%vminnm2.i = tail call <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double> %a, <2 x double> … 53 ; CHECK: fminnm d0, d0, d1 55 %vmaxnm2.i = tail call double @llvm.aarch64.neon.fminnm.f64(double %a, double %b) nounwind 59 declare <2 x double> @llvm.aarch64.neon.fminnm.v2f64(<2 x double>, <2 x double>) nounwind readnone 60 declare <4 x float> @llvm.aarch64.neon.fminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone [all …]
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D | arm64-fmax-safe.ll | 24 ; must become fminnm, not fmin. 32 ; CHECK: fminnm s
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D | arm64-neon-add-sub.ll | 212 ; CHECK: fminnm d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}} 213 %1 = tail call <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double> %a, <1 x double> %b) 232 declare <1 x double> @llvm.aarch64.neon.fminnm.v1f64(<1 x double>, <1 x double>)
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D | f16-instructions.ll | 941 ; CHECK-CVT-NEXT: fminnm s0, s0, s1 946 ; CHECK-FP16-NEXT: fminnm h0, h0, h1
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
D | neon-max-min.s | 115 fminnm v10.4h, v15.4h, v22.4h 116 fminnm v10.8h, v15.8h, v22.8h 117 fminnm v10.2s, v15.2s, v22.2s 118 fminnm v3.4s, v5.4s, v6.4s 119 fminnm v17.2d, v13.2d, v2.2d
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D | directive-cpu.s | 4 fminnm d0, d0, d1 define 8 fminnm d0, d0, d1 define
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D | directive-cpu-err.s | 12 fminnm d0, d0, d1 define
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D | arm64-fp-encoding.s | 71 fminnm h1, h2, h3 72 fminnm s1, s2, s3 73 fminnm d1, d2, d3 define 80 ; FP16: fminnm h1, h2, h3 ; encoding: [0x41,0x78,0xe3,0x1e] 82 ; NO-FP16-NEXT: fminnm h1, h2, h3 83 ; CHECK: fminnm s1, s2, s3 ; encoding: [0x41,0x78,0x23,0x1e] 84 ; CHECK: fminnm d1, d2, d3 ; encoding: [0x41,0x78,0x63,0x1e]
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D | fullfp16-neon-neg.s | 204 fminnm v10.4h, v15.4h, v22.4h 206 fminnm v10.8h, v15.8h, v22.8h
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D | arm64-advsimd.s | 322 fminnm.2s v0, v0, v0 392 ; CHECK: fminnm.2s v0, v0, v0 ; encoding: [0x00,0xc4,0xa0,0x0e] 457 fminnm.4h v0, v0, v0 482 ; CHECK: fminnm.4h v0, v0, v0 ; encoding: [0x00,0x04,0xc0,0x0e] 507 fminnm.8h v0, v0, v0 532 ; CHECK: fminnm.8h v0, v0, v0 ; encoding: [0x00,0x04,0xc0,0x4e]
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/external/capstone/suite/MC/AArch64/ |
D | neon-max-min.s.cs | 35 0xea,0xc5,0xb6,0x0e = fminnm v10.2s, v15.2s, v22.2s 36 0xa3,0xc4,0xa6,0x4e = fminnm v3.4s, v5.4s, v6.4s 37 0xb1,0xc5,0xe2,0x4e = fminnm v17.2d, v13.2d, v2.2d
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/external/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-scalar-fp.txt | 64 # FP16: fminnm h1, h2, h3 65 # CHECK: fminnm s1, s2, s3 66 # CHECK: fminnm d1, d2, d3
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
D | arm64-scalar-fp.txt | 64 # FP16: fminnm h1, h2, h3 65 # CHECK: fminnm s1, s2, s3 66 # CHECK: fminnm d1, d2, d3
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/external/vixl/doc/ |
D | changelog.md | 98 + Added support for `fmadd`, `fnmadd`, `fnmsub`, `fminnm`, `fmaxnm`,
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