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Searched refs:getDesc (Results 1 – 25 of 364) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h301 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
309 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
325 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
333 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
341 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
349 return MI.getDesc().TSFlags & SIInstrFlags::SOPK; in isSOPK()
357 return MI.getDesc().TSFlags & SIInstrFlags::SOPP; in isSOPP()
365 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()
373 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
381 return MI.getDesc().TSFlags & SIInstrFlags::VOP3; in isVOP3()
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h184 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
192 return MI.getDesc().TSFlags & SIInstrFlags::VALU; in isVALU()
208 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
216 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
224 return MI.getDesc().TSFlags & SIInstrFlags::SOPC; in isSOPC()
232 return MI.getDesc().TSFlags & SIInstrFlags::SOPK; in isSOPK()
240 return MI.getDesc().TSFlags & SIInstrFlags::SOPP; in isSOPP()
248 return MI.getDesc().TSFlags & SIInstrFlags::VOP1; in isVOP1()
256 return MI.getDesc().TSFlags & SIInstrFlags::VOP2; in isVOP2()
264 return MI.getDesc().TSFlags & SIInstrFlags::VOP3; in isVOP3()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonShuffler.cpp154 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
155 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
228 MCInst const &Inst = ISJ->getDesc(); in restrictSlot1AOK()
236 MCInst const &Inst = ISJ->getDesc(); in restrictSlot1AOK()
259 MCInst const &Inst = ISJ->getDesc(); in restrictNoSlot1Store()
268 MCInst const &Inst = ISJ->getDesc(); in restrictNoSlot1Store()
269 if (HexagonMCInstrInfo::getDesc(MCII, Inst).mayStore()) { in restrictNoSlot1Store()
313 MCInst const &ID = ISJ->getDesc(); in check()
340 if (HexagonMCInstrInfo::getDesc(MCII, ID).isReturn()) in check()
370 if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) { in check()
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DHexagonMCInstrInfo.cpp213 uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMemAccessSize()
220 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAddrMode()
225 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, in getDesc() function in HexagonMCInstrInfo
288 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
306 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
312 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
318 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in isExtentSigned()
351 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp()
376 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getNewValueOp2()
404 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits()
[all …]
DHexagonMCChecker.cpp89 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
304 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in reportBranchErrors()
315 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkHWLoop()
329 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkCOFMax1()
417 bool Branch = HexagonMCInstrInfo::getDesc(MCII, I).isBranch(); in checkNewValues()
457 HexagonMCInstrInfo::getDesc(MCII, *std::get<0>(Producer)); in checkNewValues()
498 unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs(); in checkRegistersReadOnly()
515 for (unsigned j = HexagonMCInstrInfo::getDesc(MCII, I).getNumDefs(), in registerUsed()
531 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in registerProducer()
556 HexagonMCInstrInfo::getDesc(MCII, I).mayLoad()) { in checkRegisterCurDefs()
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp134 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, Inst); in deriveExtender()
170 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getAccessSize()
178 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getBitCount()
185 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getCExtOpNum()
189 MCInstrDesc const &HexagonMCInstrInfo::getDesc(MCInstrInfo const &MCII, in getDesc() function in llvm::HexagonMCInstrInfo
251 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtendableOp()
269 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentAlignment()
275 const uint64_t F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getExtentBits()
283 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMaxValue()
298 uint64_t const F = HexagonMCInstrInfo::getDesc(MCII, MCI).TSFlags; in getMinValue()
[all …]
DHexagonShuffler.cpp132 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
133 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
195 MCInst const *ID = ISJ->getDesc(); in check()
233 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isReturn()) in check()
255 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch()) in check()
261 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) in check()
285 MCInst const *ID = ISJ->getDesc(); in check()
294 if (HexagonMCInstrInfo::getDesc(MCII, *ID).getOpcode() != Hexagon::A2_nop) in check()
304 if (HexagonMCInstrInfo::getDesc(MCII, *ID).isBranch() || in check()
305 HexagonMCInstrInfo::getDesc(MCII, *ID).isCall()) in check()
[all …]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DTargetInstrInfoImpl.cpp62 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction()
85 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) { in commuteInstruction()
89 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) { in commuteInstruction()
99 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) in commuteInstruction()
104 return BuildMI(MF, MI->getDebugLoc(), MI->getDesc()) in commuteInstruction()
124 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices()
142 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction()
221 assert(!Orig->getDesc().isNotDuplicable() && in duplicate()
291 NewMI->getDesc().mayStore()) && in foldMemoryOperand()
294 NewMI->getDesc().mayLoad()) && in foldMemoryOperand()
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DPeepholeOptimizer.cpp269 unsigned NumDefs = MI->getDesc().getNumDefs(); in OptimizeBitcastInstr()
270 unsigned NumSrcs = MI->getDesc().getNumOperands() - NumDefs; in OptimizeBitcastInstr()
295 if (!DefMI || !DefMI->getDesc().isBitcast()) in OptimizeBitcastInstr()
299 NumDefs = DefMI->getDesc().getNumDefs(); in OptimizeBitcastInstr()
300 NumSrcs = DefMI->getDesc().getNumOperands() - NumDefs; in OptimizeBitcastInstr()
355 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate()
376 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) { in FoldImmediate()
431 const MCInstrDesc &MCID = MI->getDesc(); in runOnMachineFunction()
DCriticalAntiDepBreaker.cpp57 bool IsReturnBlock = (!BB->empty() && BB->back().getDesc().isReturn()); in StartBlock()
196 bool Special = MI->getDesc().isCall() || in PrescanInstruction()
197 MI->getDesc().hasExtraSrcRegAllocReq() || in PrescanInstruction()
209 if (i < MI->getDesc().getNumOperands()) in PrescanInstruction()
210 NewRC = TII->getRegClass(MI->getDesc(), i, TRI); in PrescanInstruction()
297 if (i < MI->getDesc().getNumOperands()) in ScanInstruction()
298 NewRC = TII->getRegClass(MI->getDesc(), i, TRI); in ScanInstruction()
575 if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() || in BreakAntiDependencies()
DExecutionDepsFix.cpp313 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
314 e = mi->getDesc().getNumOperands(); i != e; ++i) { in visitHardInstr()
323 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
342 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
343 e = mi->getDesc().getNumOperands(); i != e; ++i) { in visitSoftInstr()
427 for (unsigned i = 0, e = mi->getDesc().getNumOperands(); i != e; ++i) { in visitSoftInstr()
441 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitGenericInstr()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetInstrInfo.cpp54 unsigned Class = MI->getDesc().getSchedClass(); in getNumMicroOps()
71 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency()
72 unsigned UseClass = UseMI->getDesc().getSchedClass(); in getOperandLatency()
99 return ItinData->getStageLatency(MI->getDesc().getSchedClass()); in getInstrLatency()
119 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
133 const MCInstrDesc &MCID = MI->getDesc(); in isUnpredicatedTerminator()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.cpp186 assert(LastInst.getDesc().isConditionalBranch() && in parseCondBranch()
233 if (J->getDesc().isUnconditionalBranch() || in analyzeBranch()
234 J->getDesc().isIndirectBranch()) { in analyzeBranch()
250 if (I->getDesc().isIndirectBranch()) in analyzeBranch()
258 if (NumTerminators == 1 && I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
264 if (NumTerminators == 1 && I->getDesc().isConditionalBranch()) { in analyzeBranch()
270 if (NumTerminators == 2 && std::prev(I)->getDesc().isConditionalBranch() && in analyzeBranch()
271 I->getDesc().isUnconditionalBranch()) { in analyzeBranch()
289 if (!I->getDesc().isUnconditionalBranch() && in removeBranch()
290 !I->getDesc().isConditionalBranch()) in removeBranch()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DDelaySlotFiller.cpp103 if (I->getDesc().hasDelaySlot()) { in runOnMachineBasicBlock()
152 if (slot->getDesc().isCall()) in findDelayInstr()
173 || I->getDesc().hasDelaySlot() in findDelayInstr()
197 if (candidate->getDesc().mayLoad()) { in delayHasHazard()
203 if (candidate->getDesc().mayStore()) { in delayHasHazard()
301 const MCInstrDesc &prevdesc = (--candidate)->getDesc(); in isDelayFiller()
307 if (!I->getDesc().isCall()) in needsUnimp()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeDelaySlotFiller.cpp112 MCInstrDesc desc = candidate->getDesc(); in delayHasHazard()
159 if (a_is_memory && m->getDesc().mayStore()) in delayHasHazard()
186 MCInstrDesc brdesc = (--candidate)->getDesc(); in isDelayFiller()
214 MCInstrDesc desc = I->getDesc(); in findDelayInstr()
235 if (I->getDesc().hasDelaySlot()) { in runOnMachineBasicBlock()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyCallIndirectFixup.cpp114 MI.getDesc().getNumDefs() + 1, in runOnMachineFunction()
118 Ops.push_back(MI.getOperand(MI.getDesc().getNumDefs())); in runOnMachineFunction()
121 while (MI.getNumOperands() > MI.getDesc().getNumDefs()) in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-mca/
DScheduler.cpp239 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in canBeDispatched()
264 const InstrDesc &D = IS->getDesc(); in issueInstructionImpl()
282 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in issueInstruction()
299 const InstrDesc &Desc = IS->getDesc(); in promoteToReadyQueue()
318 const InstrDesc &D = Entry.second->getDesc(); in select()
335 const InstrDesc &D = I->second->getDesc(); in select()
393 const InstrDesc &Desc = IR.getInstruction()->getDesc(); in issueImmediately()
/external/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
/external/swiftshader/third_party/LLVM/lib/Support/
DStatistic.cpp89 return std::strcmp(LHS->getDesc(), RHS->getDesc()) < 0; in operator ()()
134 << " - " << Stats.Stats[i]->getDesc() << "\n"; in PrintStatistics()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
46 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
49 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
DARMCodeEmitter.cpp450 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue()
532 switch (MI.getDesc().TSFlags & ARMII::FormMask) { in emitInstruction()
765 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction()
790 unsigned Opcode = MI.getDesc().Opcode; in emitPseudoMoveInstruction()
835 unsigned Opcode = MI.getDesc().Opcode; in emitPseudoInstruction()
1002 const MCInstrDesc &MCID = MI.getDesc(); in emitDataProcessingInstruction()
1100 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreInstruction()
1178 const MCInstrDesc &MCID = MI.getDesc(); in emitMiscLoadStoreInstruction()
1263 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreMultipleInstruction()
1303 const MCInstrDesc &MCID = MI.getDesc(); in emitMulFrmInstruction()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsDelaySlotFiller.cpp99 if (I->getDesc().hasDelaySlot()) { in runOnMachineBasicBlock()
149 || I->getDesc().isPseudo() in findDelayInstr()
177 MCInstrDesc MCID = candidate->getDesc(); in delayHasHazard()
223 MCInstrDesc MCID = MI->getDesc(); in insertDefsUses()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DTargetSchedule.cpp111 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
136 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
199 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
243 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
328 unsigned SchedClass = MI->getDesc().getSchedClass(); in computeReciprocalThroughput()
/external/skia/src/gpu/text/
DGrTextBlob.cpp411 SkASSERT_RELEASE(lRun.fDescriptor.getDesc()); in AssertEqual()
412 SkASSERT_RELEASE(rRun.fDescriptor.getDesc()); in AssertEqual()
413 SkASSERT_RELEASE(*lRun.fDescriptor.getDesc() == *rRun.fDescriptor.getDesc()); in AssertEqual()
416 SkASSERT_RELEASE(lRun.fARGBFallbackDescriptor->getDesc()); in AssertEqual()
417 … SkASSERT_RELEASE(rRun.fARGBFallbackDescriptor.get() && rRun.fARGBFallbackDescriptor->getDesc()); in AssertEqual()
418 SkASSERT_RELEASE(*lRun.fARGBFallbackDescriptor->getDesc() == in AssertEqual()
419 *rRun.fARGBFallbackDescriptor->getDesc()); in AssertEqual()

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