| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBankInfo.cpp | 35 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
46 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
58 const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID); in AArch64RegisterBankInfo()
94 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
108 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
110 return getRegBank(AArch64::CCRRegBankID); in getRegBankFromRegClass()
141 getRegBank(AArch64::GPRRegBankID)); in getInstrAlternativeMappings()
143 getRegBank(AArch64::FPRRegBankID)); in getInstrAlternativeMappings()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterBankInfo.cpp | 52 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
57 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
62 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
241 return getRegBank(AArch64::FPRRegBankID); in getRegBankFromRegClass()
255 return getRegBank(AArch64::GPRRegBankID); in getRegBankFromRegClass()
257 return getRegBank(AArch64::CCRegBankID); in getRegBankFromRegClass()
498 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
499 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
609 getRegBank(UseMI.getOperand(0).getReg(), MRI, TRI) == in getInstrMapping()
630 getRegBank(DefMI->getOperand(0).getReg(), MRI, TRI) == in getInstrMapping()
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| D | AArch64InstructionSelector.cpp | 203 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI); in unsupportedBinOp()
352 const RegisterBank &RegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
362 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
605 const RegisterBank &RB = *RBI.getRegBank(LHS, MRI, TRI); in selectCompareBranch()
810 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
1021 const RegisterBank &PtrRB = *RBI.getRegBank(PtrReg, MRI, TRI); in select()
1030 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
1084 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
1122 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
1155 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in select()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 124 const RegisterBank *RegBank = RBI.getRegBank(Reg, MRI, TRI); in guessRegClass()
178 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
183 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
188 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
209 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
214 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
219 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
408 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
750 const auto &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in select()
751 const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in select()
[all …]
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| D | ARMRegisterBankInfo.cpp | 145 const RegisterBank &RBGPR = getRegBank(ARM::GPRRegBankID); in ARMRegisterBankInfo()
185 return getRegBank(ARM::GPRRegBankID); in getRegBankFromRegClass()
192 return getRegBank(ARM::FPRRegBankID); in getRegBankFromRegClass()
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| /external/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 350 RegisterBank &getRegBank(unsigned ID) { in getRegBank() function
435 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() function
436 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); in getRegBank()
444 const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.h | 429 RegisterBank &getRegBank(unsigned ID) { in getRegBank() function
573 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank() function
574 return const_cast<RegisterBankInfo *>(this)->getRegBank(ID); in getRegBank()
582 const RegisterBank *getRegBank(unsigned Reg, const MachineRegisterInfo &MRI,
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 48 const RegisterBank &RegBank = getRegBank(Idx); in verify()
60 RegisterBank &RegBank = getRegBank(ID); in createRegisterBank()
70 RegisterBank &RB = getRegBank(ID); in addRegBankCoverage()
106 recordRegBankForType(getRegBank(ID), SVT); in addRegBankCoverage()
169 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, in getRegBank() function in RegisterBankInfo
235 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenTarget.cpp | 161 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
175 const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters(); in getRegisterByName()
185 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
187 ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses(); in getRegisterVTs()
204 ArrayRef<CodeGenRegisterClass*> RCs = getRegBank().getRegClasses(); in ReadLegalValueTypes()
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| D | CodeGenTarget.h | 99 CodeGenRegBank &getRegBank() const;
111 return *getRegBank().getRegClass(R); in getRegisterClass()
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| D | DAGISelMatcherGen.cpp | 28 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
29 ArrayRef<CodeGenRegisterClass*> RCs = T.getRegBank().getRegClasses(); in getRegisterValueType()
586 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterBankInfo.cpp | 33 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo()
51 return getRegBank(X86::GPRRegBankID); in getRegBankFromRegClass()
58 return getRegBank(X86::VECRRegBankID); in getRegBankFromRegClass()
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| D | X86InstructionSelector.cpp | 199 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
235 const RegisterBank &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectCopy()
239 const RegisterBank &SrcRegBank = *RBI.getRegBank(SrcReg, MRI, TRI); in selectCopy()
502 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
623 if (RBI.getRegBank(DefReg, MRI, TRI)->getID() != X86::GPRRegBankID) in selectConstant()
699 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
700 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
788 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectZext()
789 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectZext()
874 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 45 const RegisterBank &RBSGPR = getRegBank(AMDGPU::SGPRRegBankID); in AMDGPURegisterBankInfo()
49 const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID); in AMDGPURegisterBankInfo()
93 return getRegBank(AMDGPU::SGPRRegBankID); in getRegBankFromRegClass()
95 return getRegBank(AMDGPU::VGPRRegBankID); in getRegBankFromRegClass()
197 const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI); in isSALUMapping()
283 const RegisterBank *Bank = getRegBank(Reg, MRI, TRI); in getRegBankID()
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| /external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/ |
| D | CodeGenTarget.h | 105 CodeGenRegBank &getRegBank() const;
117 return *getRegBank().getRegClass(R); in getRegisterClass()
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| D | CodeGenTarget.cpp | 273 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
287 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); in getRegisterByName()
296 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
298 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
313 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
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| D | DAGISelMatcherGen.cpp | 28 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
30 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
624 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenTarget.h | 114 CodeGenRegBank &getRegBank() const;
126 return *getRegBank().getRegClass(R); in getRegisterClass()
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| D | CodeGenTarget.cpp | 221 CodeGenRegBank &CodeGenTarget::getRegBank() const { in getRegBank() function in CodeGenTarget
235 const StringMap<CodeGenRegister*> &Regs = getRegBank().getRegistersByName(); in getRegisterByName()
244 const CodeGenRegister *Reg = getRegBank().getReg(R); in getRegisterVTs()
246 for (const auto &RC : getRegBank().getRegClasses()) { in getRegisterVTs()
261 for (const auto &RC : getRegBank().getRegClasses()) in ReadLegalValueTypes()
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| D | DAGISelMatcherGen.cpp | 28 const CodeGenRegister *Reg = T.getRegBank().getReg(R); in getRegisterValueType()
30 for (const auto &RC : T.getRegBank().getRegClasses()) { in getRegisterValueType()
619 CGP.getTargetInfo().getRegBank().getReg(Def); in EmitResultLeafAsOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterBankInfo.cpp | 62 return getRegBank(Mips::GPRBRegBankID); in getRegBankFromRegClass()
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| D | MipsInstructionSelector.cpp | 132 const unsigned DestRegBank = RBI.getRegBank(DestReg, MRI, TRI)->getID(); in select()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 73 const RegisterBank &RegBank = getRegBank(Idx); in verify()
84 RegisterBankInfo::getRegBank(unsigned Reg, const MachineRegisterInfo &MRI, in getRegBank() function in RegisterBankInfo
192 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
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| /external/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 162 const RegisterBank *getRegBank(const MachineFunction &MF, StringRef Name);
380 const auto *RegBank = getRegBank(MF, VReg.Class.Value); in initializeRegisterInfo()
736 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks()
751 const RegisterBank *MIRParserImpl::getRegBank(const MachineFunction &MF, in getRegBank() function in MIRParserImpl
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/MIRParser/ |
| D | MIRParser.cpp | 166 const RegisterBank *getRegBank(const MachineFunction &MF, StringRef Name);
456 const RegisterBank *RegBank = getRegBank(MF, VReg.Class.Value); in parseRegisterInfo()
865 const auto &RegBank = RBI->getRegBank(I); in initNames2RegBanks()
879 const RegisterBank *MIRParserImpl::getRegBank(const MachineFunction &MF, in getRegBank() function in MIRParserImpl
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