| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 83 I->getRegClassConstraint(I.getOperandNo(), TII, TRI); in recomputeRegClass()
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| D | MachineInstr.cpp | 858 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() function in MachineInstr
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineInstr.h | 412 getRegClassConstraint(unsigned OpIdx,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineCopyPropagation.cpp | 262 UseI.getRegClassConstraint(UseIdx, TII, TRI)) in isForwardableRegClassCopy()
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| D | MachineInstr.cpp | 650 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() function in MachineInstr
721 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect()
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| D | TailDuplicator.cpp | 434 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction()
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| D | TargetInstrInfo.cpp | 784 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); in reassociateOps()
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| /external/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 190 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); in getRegBankFromConstraints()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 993 getRegClassConstraint(unsigned OpIdx,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 116 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI); in getRegBankFromConstraints()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 1081 getRegClassConstraint(unsigned OpIdx,
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| /external/llvm/lib/CodeGen/ |
| D | TailDuplicator.cpp | 392 auto *NewRC = MI->getRegClassConstraint(i, TII, TRI); in duplicateInstruction()
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| D | MachineInstr.cpp | 1178 MachineInstr::getRegClassConstraint(unsigned OpIdx, in getRegClassConstraint() function in MachineInstr
1246 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI); in getRegClassConstraintEffect()
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| D | TargetInstrInfo.cpp | 674 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI); in reassociateOps()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 760 Instr.getRegClassConstraint(OpIdx, TII, TRI); in UpdateOperandRegClass()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1187 Instr.getRegClassConstraint(OpIdx, TII, TRI); in UpdateOperandRegClass()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2637 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI); in verifyInstruction()
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