| /external/mesa3d/src/amd/addrlib/ |
| D | meson.build | 36 'gfx9/chip/gfx9_enum.h',
37 'gfx9/coord.cpp',
38 'gfx9/coord.h',
39 'gfx9/gfx9addrlib.cpp',
40 'gfx9/gfx9addrlib.h',
42 'inc/chip/gfx9/gfx9_gb_reg.h',
58 'core', 'inc/chip/gfx9', 'inc/chip/r800', 'gfx9/chip', 'r800/chip',
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| /external/mesa3d/src/amd/common/ |
| D | ac_surface.c | 867 surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode; in gfx9_compute_miptree()
868 surf->u.gfx9.stencil.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 : in gfx9_compute_miptree()
871 surf->u.gfx9.stencil_offset = align(surf->surf_size, out.baseAlign); in gfx9_compute_miptree()
872 surf->surf_size = surf->u.gfx9.stencil_offset + out.surfSize; in gfx9_compute_miptree()
876 surf->u.gfx9.surf.swizzle_mode = in->swizzleMode; in gfx9_compute_miptree()
877 surf->u.gfx9.surf.epitch = out.epitchIsHeight ? out.mipChainHeight - 1 : in gfx9_compute_miptree()
883 surf->u.gfx9.fmask.swizzle_mode = surf->u.gfx9.surf.swizzle_mode & ~0x3; in gfx9_compute_miptree()
884 surf->u.gfx9.fmask.epitch = surf->u.gfx9.surf.epitch; in gfx9_compute_miptree()
886 surf->u.gfx9.surf_slice_size = out.sliceSize; in gfx9_compute_miptree()
887 surf->u.gfx9.surf_pitch = out.pitch; in gfx9_compute_miptree()
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| D | ac_surface.h | 209 struct gfx9_surf_layout gfx9; member
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| /external/mesa3d/src/amd/ |
| D | Makefile.sources | 23 addrlib/gfx9/chip/gfx9_enum.h \
24 addrlib/gfx9/coord.cpp \
25 addrlib/gfx9/coord.h \
26 addrlib/gfx9/gfx9addrlib.cpp \
27 addrlib/gfx9/gfx9addrlib.h \
28 addrlib/inc/chip/gfx9/gfx9_gb_reg.h \
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| D | Android.addrlib.mk | 38 $(MESA_TOP)/src/amd/addrlib/inc/chip/gfx9 \
40 $(MESA_TOP)/src/amd/addrlib/gfx9/chip \
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| D | Makefile.addrlib.am | 29 -I$(srcdir)/addrlib/inc/chip/gfx9 \
31 -I$(srcdir)/addrlib/gfx9/chip \
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 251 va += image->surface.u.gfx9.stencil_offset; in si_set_mutable_tex_desc_fields()
253 va += image->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
288 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.stencil.swizzle_mode); in si_set_mutable_tex_desc_fields()
289 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.stencil.epitch); in si_set_mutable_tex_desc_fields()
291 state[3] |= S_008F1C_SW_MODE(image->surface.u.gfx9.surf.swizzle_mode); in si_set_mutable_tex_desc_fields()
292 state[4] |= S_008F20_PITCH_GFX9(image->surface.u.gfx9.surf.epitch); in si_set_mutable_tex_desc_fields()
302 meta = image->surface.u.gfx9.dcc; in si_set_mutable_tex_desc_fields()
304 meta = image->surface.u.gfx9.htile; in si_set_mutable_tex_desc_fields()
323 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9) in radv_tex_dim() argument
329 if (gfx9 && image_type == VK_IMAGE_TYPE_1D) in radv_tex_dim()
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| D | radv_device.c | 3109 meta = iview->image->surface.u.gfx9.dcc; in radv_initialise_color_surface()
3111 meta = iview->image->surface.u.gfx9.cmask; in radv_initialise_color_surface()
3113 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) | in radv_initialise_color_surface()
3114 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) | in radv_initialise_color_surface()
3118 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8; in radv_initialise_color_surface()
3284 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type); in radv_initialise_color_surface()
3340 assert(iview->image->surface.u.gfx9.surf_offset == 0); in radv_initialise_ds_surface()
3341 s_offs += iview->image->surface.u.gfx9.stencil_offset; in radv_initialise_ds_surface()
3345 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) | in radv_initialise_ds_surface()
3348 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode); in radv_initialise_ds_surface()
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| D | radv_radeon_winsys.h | 148 } gfx9; member
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_texture.c | 188 *stride = rtex->surface.u.gfx9.surf_pitch * rtex->surface.bpe; in r600_texture_get_offset()
189 *layer_stride = rtex->surface.u.gfx9.surf_slice_size; in r600_texture_get_offset()
196 return box->z * rtex->surface.u.gfx9.surf_slice_size + in r600_texture_get_offset()
197 rtex->surface.u.gfx9.offset[level] + in r600_texture_get_offset()
199 rtex->surface.u.gfx9.surf_pitch + in r600_texture_get_offset()
305 surface->u.gfx9.surf_pitch = pitch; in r600_init_surface()
306 surface->u.gfx9.surf_slice_size = in r600_init_surface()
307 (uint64_t)pitch * surface->u.gfx9.surf_height * bpe; in r600_init_surface()
309 surface->u.gfx9.surf_offset = offset; in r600_init_surface()
333 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode; in r600_texture_init_metadata()
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| D | radeon_video.c | 178 surfaces[i]->u.gfx9.surf_offset += off; in si_vid_join_surfaces()
179 for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.gfx9.offset); ++j) in si_vid_join_surfaces()
180 surfaces[i]->u.gfx9.offset[j] += off; in si_vid_join_surfaces()
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| D | radeon_vce_52.c | 187 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encRefPicLumaPitch in create()
188 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encRefPicChromaPitch in create()
189 RVCE_CS(align(enc->luma->u.gfx9.surf_height, 16) / 8); // encRefYHeightInQw in create()
263 enc->luma->u.gfx9.surf_offset); // inputPictureLumaAddressHi/Lo in encode()
265 enc->chroma->u.gfx9.surf_offset); // inputPictureChromaAddressHi/Lo in encode()
266 RVCE_CS(align(enc->luma->u.gfx9.surf_height, 16)); // encInputFrameYPitch in encode()
267 RVCE_CS(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe); // encInputPicLumaPitch in encode()
268 RVCE_CS(enc->chroma->u.gfx9.surf_pitch * enc->chroma->bpe); // encInputPicChromaPitch in encode()
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| D | radeon_vce.c | 229 pitch = align(enc->luma->u.gfx9.surf_pitch * enc->luma->bpe, 256); in si_vce_frame_offset()
230 vpitch = align(enc->luma->u.gfx9.surf_height, 16); in si_vce_frame_offset()
466 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in si_vce_create_encoder()
467 align(tmp_surf->u.gfx9.surf_height, 32); in si_vce_create_encoder()
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| D | radeon_vcn_enc.c | 281 align(tmp_surf->u.gfx9.surf_pitch * tmp_surf->bpe, 256) * in radeon_create_encoder()
282 align(tmp_surf->u.gfx9.surf_height, 32); in radeon_create_encoder()
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| D | radeon_vcn_dec.c | 661 decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w; in rvcn_dec_message_decode()
671 decode->dt_luma_top_offset = luma->surface.u.gfx9.surf_offset; in rvcn_dec_message_decode()
672 decode->dt_chroma_top_offset = chroma->surface.u.gfx9.surf_offset; in rvcn_dec_message_decode()
674 decode->dt_luma_bottom_offset = luma->surface.u.gfx9.surf_offset + in rvcn_dec_message_decode()
675 luma->surface.u.gfx9.surf_slice_size; in rvcn_dec_message_decode()
676 decode->dt_chroma_bottom_offset = chroma->surface.u.gfx9.surf_offset + in rvcn_dec_message_decode()
677 chroma->surface.u.gfx9.surf_slice_size; in rvcn_dec_message_decode()
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| D | radeon_vcn_enc_1_2.c | 709 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch; in radeon_enc_encode_params()
710 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch; in radeon_enc_encode_params()
723 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_enc_encode_params()
724 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_enc_encode_params()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_clear.c | 254 assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4); in si_set_optimal_micro_tile_mode()
264 assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0); in si_set_optimal_micro_tile_mode()
268 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
269 rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */ in si_set_optimal_micro_tile_mode()
272 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
273 rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */ in si_set_optimal_micro_tile_mode()
276 rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3; in si_set_optimal_micro_tile_mode()
277 rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */ in si_set_optimal_micro_tile_mode()
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| D | si_state.c | 1934 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) { in si_tex_dim()
2489 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type); in si_initialize_color_surface()
2527 assert(rtex->surface.u.gfx9.surf_offset == 0); in si_init_depth_surface()
2530 rtex->surface.u.gfx9.stencil_offset) >> 8; in si_init_depth_surface()
2533 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) | in si_init_depth_surface()
2536 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode); in si_init_depth_surface()
2537 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch); in si_init_depth_surface()
2538 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch); in si_init_depth_surface()
2572 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) | in si_init_depth_surface()
2573 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned); in si_init_depth_surface()
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| D | si_descriptors.c | 330 va += tex->surface.u.gfx9.stencil_offset; in si_set_mutable_tex_desc_fields()
332 va += tex->surface.u.gfx9.surf_offset; in si_set_mutable_tex_desc_fields()
377 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode); in si_set_mutable_tex_desc_fields()
378 state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.stencil.epitch); in si_set_mutable_tex_desc_fields()
380 state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode); in si_set_mutable_tex_desc_fields()
381 state[4] |= S_008F20_PITCH_GFX9(tex->surface.u.gfx9.surf.epitch); in si_set_mutable_tex_desc_fields()
391 meta = tex->surface.u.gfx9.dcc; in si_set_mutable_tex_desc_fields()
393 meta = tex->surface.u.gfx9.htile; in si_set_mutable_tex_desc_fields()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | store-hi16.ll | 18 ; FIXME: ABI for pre-gfx9
38 ; FIXME: ABI for pre-gfx9
119 ; FIXME: ABI for pre-gfx9
401 ; FIXME: ABI for pre-gfx9
420 ; FIXME: ABI for pre-gfx9
514 ; FIXME: ABI for pre-gfx9
553 ; FIXME: ABI for pre-gfx9
572 ; FIXME: ABI for pre-gfx9
627 ; FIXME: ABI for pre-gfx9
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| D | amdpal_scratch_mergedshader.ll | 3 ; On gfx9 and later, a HS is a merged shader, in which s0-s7 are reserved by the
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| D | mul.i16.ll | 60 ; FIXME: Unpack garbage on gfx9
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUUsage.rst | 1608 :name: amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table
1646 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`.
1653 … :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`.
1681 :name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table
1911 :name: amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table
2453 :ref:`amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table`.
2595 :name: amdgpu-amdhsa-memory-model-code-sequences-gfx6-gfx9-table
3800 :ref:`amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table`.
3803 :name: amdgpu-amdhsa-memory-model-single-thread-optimization-constraints-gfx6-gfx9-table
4485 … :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`.
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/Inline/AMDGPU/ |
| D | inline-target-cpu.ll | 35 ; Make sure gfx9 can call unspecified functions because of movrel
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| /external/mesa3d/bin/ |
| D | .cherry-ignore | 26 d15fb766aa3c98ffbe16d050b2af4804e4b12c57 radeonsi/gfx9: fix a hang with an empty first IB
|