Searched refs:htile_offset (Results 1 – 14 of 14) sorted by relevance
| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_texture.c | 558 rtex->htile_offset = new_tex->htile_offset; in r600_reallocate_texture_inplace()
566 assert(!rtex->htile_offset); in r600_reallocate_texture_inplace()
1040 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment); in r600_texture_allocate_htile()
1041 rtex->size = rtex->htile_offset + rtex->surface.htile_size; in r600_texture_allocate_htile()
1090 if (rtex->htile_offset) { in si_print_texture_info()
1093 rtex->htile_offset, in si_print_texture_info()
1138 if (rtex->htile_offset) in si_print_texture_info()
1141 rtex->htile_offset, rtex->surface.htile_size, in si_print_texture_info()
1318 if (rtex->htile_offset) { in r600_texture_create_object()
1325 rtex->htile_offset, in r600_texture_create_object()
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| D | r600_pipe_common.h | 227 uint64_t htile_offset; member
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| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_texture.c | 427 rtex->htile_offset = new_tex->htile_offset; in r600_reallocate_texture_inplace()
434 assert(!rtex->htile_offset); in r600_reallocate_texture_inplace()
800 rtex->htile_offset = align(rtex->size, rtex->surface.htile_alignment); in r600_texture_allocate_htile()
801 rtex->size = rtex->htile_offset + rtex->surface.htile_size; in r600_texture_allocate_htile()
840 if (rtex->htile_offset) in r600_print_texture_info()
843 rtex->htile_offset, rtex->surface.htile_size, in r600_print_texture_info()
982 if (rtex->htile_offset) { in r600_texture_create_object()
986 rtex->htile_offset, in r600_texture_create_object()
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| D | r600_pipe_common.h | 231 uint64_t htile_offset; member
916 return tex->htile_offset && level == 0; in r600_htile_enabled()
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| D | r600_state.c | 1073 surf->db_htile_data_base = rtex->htile_offset >> 8; in r600_init_depth_surface()
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| D | evergreen_state.c | 1418 uint64_t va = rtex->resource.gpu_address + rtex->htile_offset; in evergreen_init_depth_surface()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_pipe.h | 917 return tex->htile_offset && level == 0; in si_htile_enabled()
923 assert(!tex->tc_compatible_htile || tex->htile_offset); in vi_tc_compat_htile_enabled()
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| D | si_state.c | 2570 rtex->htile_offset) >> 8; in si_init_depth_surface()
2648 rtex->htile_offset) >> 8; in si_init_depth_surface()
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| D | si_descriptors.c | 363 meta_va = tex->resource.gpu_address + tex->htile_offset; in si_set_mutable_tex_desc_fields()
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| /external/mesa3d/src/amd/vulkan/ |
| D | radv_image.c | 273 meta_va = gpu_address + image->htile_offset; in si_set_mutable_tex_desc_fields()
808 image->htile_offset = align64(image->size, image->surface.htile_alignment); in radv_image_alloc_htile()
811 image->clear_value_offset = image->htile_offset + image->surface.htile_size; in radv_image_alloc_htile()
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| D | radv_private.h | 1380 uint64_t htile_offset; member
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| D | radv_meta_clear.c | 736 iview->image->offset + iview->image->htile_offset, in emit_fast_htile_clear()
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| D | radv_device.c | 3376 iview->image->htile_offset; in radv_initialise_ds_surface()
3441 iview->image->htile_offset; in radv_initialise_ds_surface()
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| D | radv_cmd_buffer.c | 3902 uint64_t offset = image->offset + image->htile_offset + in radv_initialize_htile()
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