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Searched refs:i32x4 (Results 1 – 16 of 16) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/WebAssembly/
Dsimd-arith.ll91 ; NO-SIMD128-NOT: i32x4
94 ; SIMD128: i32x4.add $push0=, $0, $1{{$}}
102 ; NO-SIMD128-NOT: i32x4
105 ; SIMD128: i32x4.sub $push0=, $0, $1{{$}}
113 ; NO-SIMD128-NOT: i32x4
116 ; SIMD128: i32x4.mul $push0=, $0, $1{{$}}
/external/v8/src/wasm/
Dwasm-interpreter.cc1709 EXTRACT_LANE_CASE(I32x4, i32x4) in ExecuteSimdOp()
1734 BINOP_CASE(I32x4Add, i32x4, int4, 4, a + b) in ExecuteSimdOp()
1735 BINOP_CASE(I32x4Sub, i32x4, int4, 4, a - b) in ExecuteSimdOp()
1736 BINOP_CASE(I32x4Mul, i32x4, int4, 4, a * b) in ExecuteSimdOp()
1737 BINOP_CASE(I32x4MinS, i32x4, int4, 4, a < b ? a : b) in ExecuteSimdOp()
1738 BINOP_CASE(I32x4MinU, i32x4, int4, 4, in ExecuteSimdOp()
1740 BINOP_CASE(I32x4MaxS, i32x4, int4, 4, a > b ? a : b) in ExecuteSimdOp()
1741 BINOP_CASE(I32x4MaxU, i32x4, int4, 4, in ExecuteSimdOp()
1743 BINOP_CASE(S128And, i32x4, int4, 4, a & b) in ExecuteSimdOp()
1744 BINOP_CASE(S128Or, i32x4, int4, 4, a | b) in ExecuteSimdOp()
[all …]
Dwasm-value.h19 V(int32_t, int4, i32x4, 4) \
/external/mesa3d/src/gallium/auxiliary/gallivm/
Dlp_bld_format_cached.c154 LLVMTypeRef i32x4 = LLVMVectorType(LLVMInt32TypeInContext(gallivm->context), 4); in update_cached_block() local
196 tmp_ptr = lp_build_array_alloca(gallivm, i32x4, in update_cached_block()
225 tmp_ptr = LLVMBuildBitCast(builder, tmp_ptr, LLVMPointerType(i32x4, 0), ""); in update_cached_block()
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/WebAssembly/
Dbasic-assembly.s8 .local f32, f64 #, i8x16, i16x8, i32x4, f32x4
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFormats.td138 !strconcat("i32x4.",
140 !strconcat("i32x4.", name)>;
DWebAssemblyInstrCall.td93 defm "" : SIMD_CALL<v4i32, "i32x4.">;
/external/llvm/test/CodeGen/X86/
Davx512-intrinsics.ll4888 declare <16 x i32> @llvm.x86.avx512.mask.shuf.i32x4(<16 x i32>, <16 x i32>, i32, <16 x i32>, i16)
4898 …%res = call <16 x i32> @llvm.x86.avx512.mask.shuf.i32x4(<16 x i32> %x0, <16 x i32> %x1, i32 22, <1…
4899 …%res1 = call <16 x i32> @llvm.x86.avx512.mask.shuf.i32x4(<16 x i32> %x0, <16 x i32> %x1, i32 22, <…
Davx512vl-intrinsics.ll4420 declare <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32>, <8 x i32>, i32, <8 x i32>, i8)
4432 …%res = call <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <…
4433 …%res1 = call <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, …
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Davx512-intrinsics-upgrade.ll2727 declare <16 x i32> @llvm.x86.avx512.mask.shuf.i32x4(<16 x i32>, <16 x i32>, i32, <16 x i32>, i16)
2749 …%res = call <16 x i32> @llvm.x86.avx512.mask.shuf.i32x4(<16 x i32> %x0, <16 x i32> %x1, i32 22, <1…
2750 …%res1 = call <16 x i32> @llvm.x86.avx512.mask.shuf.i32x4(<16 x i32> %x0, <16 x i32> %x1, i32 22, <…
Davx512vl-intrinsics-upgrade.ll5244 declare <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32>, <8 x i32>, i32, <8 x i32>, i8)
5265 …%res = call <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, <…
5266 …%res1 = call <8 x i32> @llvm.x86.avx512.mask.shuf.i32x4.256(<8 x i32> %x0, <8 x i32> %x1, i32 22, …
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen5220 x86_avx512_mask_shuf_i32x4, // llvm.x86.avx512.mask.shuf.i32x4
5221 x86_avx512_mask_shuf_i32x4_256, // llvm.x86.avx512.mask.shuf.i32x4.256
11278 "llvm.x86.avx512.mask.shuf.i32x4",
11279 "llvm.x86.avx512.mask.shuf.i32x4.256",
19218 1, // llvm.x86.avx512.mask.shuf.i32x4
19219 1, // llvm.x86.avx512.mask.shuf.i32x4.256
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen5220 x86_avx512_mask_shuf_i32x4, // llvm.x86.avx512.mask.shuf.i32x4
5221 x86_avx512_mask_shuf_i32x4_256, // llvm.x86.avx512.mask.shuf.i32x4.256
11278 "llvm.x86.avx512.mask.shuf.i32x4",
11279 "llvm.x86.avx512.mask.shuf.i32x4.256",
19218 1, // llvm.x86.avx512.mask.shuf.i32x4
19219 1, // llvm.x86.avx512.mask.shuf.i32x4.256
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen5220 x86_avx512_mask_shuf_i32x4, // llvm.x86.avx512.mask.shuf.i32x4
5221 x86_avx512_mask_shuf_i32x4_256, // llvm.x86.avx512.mask.shuf.i32x4.256
11278 "llvm.x86.avx512.mask.shuf.i32x4",
11279 "llvm.x86.avx512.mask.shuf.i32x4.256",
19218 1, // llvm.x86.avx512.mask.shuf.i32x4
19219 1, // llvm.x86.avx512.mask.shuf.i32x4.256
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen5196 x86_avx512_mask_shuf_i32x4, // llvm.x86.avx512.mask.shuf.i32x4
5197 x86_avx512_mask_shuf_i32x4_256, // llvm.x86.avx512.mask.shuf.i32x4.256
11220 "llvm.x86.avx512.mask.shuf.i32x4",
11221 "llvm.x86.avx512.mask.shuf.i32x4.256",
19105 1, // llvm.x86.avx512.mask.shuf.i32x4
19106 1, // llvm.x86.avx512.mask.shuf.i32x4.256
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen5220 x86_avx512_mask_shuf_i32x4, // llvm.x86.avx512.mask.shuf.i32x4
5221 x86_avx512_mask_shuf_i32x4_256, // llvm.x86.avx512.mask.shuf.i32x4.256
11278 "llvm.x86.avx512.mask.shuf.i32x4",
11279 "llvm.x86.avx512.mask.shuf.i32x4.256",
19218 1, // llvm.x86.avx512.mask.shuf.i32x4
19219 1, // llvm.x86.avx512.mask.shuf.i32x4.256