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/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dapint-and1.ll37 define i7 @test5(i7 %A, i7* %P) {
38 %B = or i7 %A, 3
39 %C = xor i7 %B, 12
40 store i7 %C, i7* %P
41 %r = and i7 %C, 3
42 ret i7 %r
45 define i7 @test6(i7 %A, i7 %B) {
47 %t0 = xor i7 %A, -1
48 %t1 = and i7 %t0, %B
49 %r = xor i7 %t1, -1
[all …]
Dapint-xor1.ll32 define i7 @test5(i7 %A) {
34 %t1 = or i7 %A, 23
35 %r = xor i7 %t1, 23
36 ret i7 %r
39 define i7 @test6(i7 %A) {
40 %t1 = xor i7 %A, 23
41 %r = xor i7 %t1, 23
42 ret i7 %r
Dapint-call-cast-target.ll9 %tmp = call i32 bitcast (i7* (i999*)* @ctime to i32 (i99*)*)( i99* null )
13 define i7* @ctime(i999*) {
15 %tmp = call i7* bitcast (i32 ()* @main to i7* ()*)( )
16 ret i7* %tmp
Dapint-and-or-and.ll45 define i7 @or_test2(i7 %X, i7 %Y) {
46 %A = shl i7 %X, 6
47 %B = or i7 %A, 64 ;; This cannot include any bits from X!
48 ret i7 %B
Dapint-shift.ll11 define i41 @test2(i7 %X) {
12 %A = zext i7 %X to i41 ; <i41> [#uses=1]
22 define i39 @test4(i7 %X) {
23 %A = zext i7 %X to i39 ; <i39> [#uses=1]
50 define i7 @test8(i7 %A) {
51 %B = shl i7 %A, 4 ; <i7> [#uses=1]
52 %C = shl i7 %B, 3 ; <i7> [#uses=1]
53 ret i7 %C
/external/llvm/test/Transforms/InstCombine/
Dapint-and1.ll37 define i7 @test5(i7 %A, i7* %P) {
38 %B = or i7 %A, 3
39 %C = xor i7 %B, 12
40 store i7 %C, i7* %P
41 %r = and i7 %C, 3
42 ret i7 %r
45 define i7 @test6(i7 %A, i7 %B) {
47 %t0 = xor i7 %A, -1
48 %t1 = and i7 %t0, %B
49 %r = xor i7 %t1, -1
[all …]
Dapint-call-cast-target.ll8 ; CHECK: %[[call:.*]] = call i7* @ctime(i999* null)
9 ; CHECK: %[[cast:.*]] = ptrtoint i7* %[[call]] to i32
12 %tmp = call i32 bitcast (i7* (i999*)* @ctime to i32 (i99*)*)( i99* null )
16 define i7* @ctime(i999*) {
17 ; CHECK-LABEL: define i7* @ctime(
19 ; CHECK: %[[cast:.*]] = inttoptr i32 %[[call]] to i7*
21 %tmp = call i7* bitcast (i32 ()* @main to i7* ()*)( )
22 ret i7* %tmp
Dapint-xor1.ll32 define i7 @test5(i7 %A) {
34 %t1 = or i7 %A, 23
35 %r = xor i7 %t1, 23
36 ret i7 %r
39 define i7 @test6(i7 %A) {
40 %t1 = xor i7 %A, 23
41 %r = xor i7 %t1, 23
42 ret i7 %r
Dapint-and-or-and.ll45 define i7 @or_test2(i7 %X, i7 %Y) {
46 %A = shl i7 %X, 6
47 %B = or i7 %A, 64 ;; This cannot include any bits from X!
48 ret i7 %B
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Sparc/
Dsparc-coproc.s6 ! CHECK: ld [%i7], %c4 ! encoding: [0xc9,0x87,0xc0,0x00]
11 ld [%i7], %c4
16 ! CHECK: ldd [%i7], %c4 ! encoding: [0xc9,0x9f,0xc0,0x00]
17 ! CHECK: ldd [%i7+200], %c4 ! encoding: [0xc9,0x9f,0xe0,0xc8]
18 ! CHECK: ldd [%i7+%o3], %c4 ! encoding: [0xc9,0x9f,0xc0,0x0b]
21 ldd [%i7], %c4
22 ldd [%i7 + 200], %c4
23 ldd [%i7+%o3], %c4
28 ! CHECK: st %c4, [%i7] ! encoding: [0xc9,0xa7,0xc0,0x00]
29 ! CHECK: st %c4, [%i7+48] ! encoding: [0xc9,0xa7,0xe0,0x30]
[all …]
/external/llvm/test/MC/Sparc/
Dsparc-coproc.s6 ! CHECK: ld [%i7], %c4 ! encoding: [0xc9,0x87,0xc0,0x00]
11 ld [%i7], %c4
16 ! CHECK: ldd [%i7], %c4 ! encoding: [0xc9,0x9f,0xc0,0x00]
17 ! CHECK: ldd [%i7+200], %c4 ! encoding: [0xc9,0x9f,0xe0,0xc8]
18 ! CHECK: ldd [%i7+%o3], %c4 ! encoding: [0xc9,0x9f,0xc0,0x0b]
21 ldd [%i7], %c4
22 ldd [%i7 + 200], %c4
23 ldd [%i7+%o3], %c4
28 ! CHECK: st %c4, [%i7] ! encoding: [0xc9,0xa7,0xc0,0x00]
29 ! CHECK: st %c4, [%i7+48] ! encoding: [0xc9,0xa7,0xe0,0x30]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dapint-call-cast-target.ll8 ; CHECK: %[[call:.*]] = call i7* @ctime(i999* null)
9 ; CHECK: %[[cast:.*]] = ptrtoint i7* %[[call]] to i32
12 %tmp = call i32 bitcast (i7* (i999*)* @ctime to i32 (i99*)*)( i99* null )
16 define i7* @ctime(i999*) {
17 ; CHECK-LABEL: define i7* @ctime(
19 ; CHECK: %[[cast:.*]] = inttoptr i32 %[[call]] to i7*
21 %tmp = call i7* bitcast (i32 ()* @main to i7* ()*)( )
22 ret i7* %tmp
Dapint-xor1.ll32 define i7 @test5(i7 %A) {
34 %t1 = or i7 %A, 23
35 %r = xor i7 %t1, 23
36 ret i7 %r
39 define i7 @test6(i7 %A) {
40 %t1 = xor i7 %A, 23
41 %r = xor i7 %t1, 23
42 ret i7 %r
Dapint-and.ll42 define i7 @test5(i7 %A, i7* %P) {
44 ; CHECK-NEXT: [[B:%.*]] = or i7 %A, 3
45 ; CHECK-NEXT: [[C:%.*]] = xor i7 [[B]], 12
46 ; CHECK-NEXT: store i7 [[C]], i7* %P, align 1
47 ; CHECK-NEXT: ret i7 3
49 %B = or i7 %A, 3
50 %C = xor i7 %B, 12
51 store i7 %C, i7* %P
52 %r = and i7 %C, 3
53 ret i7 %r
Dapint-shift.ll49 define i7 @test8(i7 %A) {
51 ; CHECK-NEXT: ret i7 0
53 %B = shl i7 %A, 4
54 %C = shl i7 %B, 3
55 ret i7 %C
187 define <2 x i7> @lshr_shl_splat_vec(<2 x i7> %X) {
189 ; CHECK-NEXT: [[MUL:%.*]] = mul <2 x i7> %X, <i7 -8, i7 -8>
190 ; CHECK-NEXT: [[SH1:%.*]] = lshr exact <2 x i7> [[MUL]], <i7 1, i7 1>
191 ; CHECK-NEXT: ret <2 x i7> [[SH1]]
193 %mul = mul <2 x i7> %X, <i7 -8, i7 -8>
[all …]
Dapint-add.ll57 define i7 @sext(i4 %x) {
59 ; CHECK-NEXT: [[ADD:%.*]] = sext i4 %x to i7
60 ; CHECK-NEXT: ret i7 [[ADD]]
63 %zext = zext i4 %xor to i7
64 %add = add nsw i7 %zext, -8
65 ret i7 %add
84 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i4 [[XOR]] to i7
85 ; CHECK-NEXT: [[ADD:%.*]] = sext i4 %x to i7
86 ; CHECK-NEXT: [[MUL:%.*]] = sdiv i7 [[ZEXT]], [[ADD]]
87 ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i7 [[MUL]] to i4
[all …]
Dapint-and-or-and.ll45 define i7 @or_test2(i7 %X, i7 %Y) {
46 %A = shl i7 %X, 6
47 %B = or i7 %A, 64 ;; This cannot include any bits from X!
48 ret i7 %B
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dfunnel-shift.ll66 declare i7 @llvm.fshl.i7(i7, i7, i7)
67 define i7 @fshl_i7_const_fold() {
72 %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
73 ret i7 %f
178 declare i7 @llvm.fshr.i7(i7, i7, i7)
179 define i7 @fshr_i7_const_fold() {
184 %f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
185 ret i7 %f
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/
Dresched.ll96 …%arrayidx.i.i7.1.i.i = getelementptr inbounds %"struct.std::array", %"struct.std::array"* undef, i…
97 store i8 %conv.1.i.i, i8* %arrayidx.i.i7.1.i.i, align 1
101 …%arrayidx.i.i7.2.i.i = getelementptr inbounds %"struct.std::array", %"struct.std::array"* undef, i…
102 store i8 %conv.2.i.i, i8* %arrayidx.i.i7.2.i.i, align 1
106 …%arrayidx.i.i7.3.i.i = getelementptr inbounds %"struct.std::array", %"struct.std::array"* undef, i…
107 store i8 %conv.3.i.i, i8* %arrayidx.i.i7.3.i.i, align 1
111 …%arrayidx.i.i7.4.i.i = getelementptr inbounds %"struct.std::array", %"struct.std::array"* undef, i…
112 store i8 %conv.4.i.i, i8* %arrayidx.i.i7.4.i.i, align 1
116 …%arrayidx.i.i7.5.i.i = getelementptr inbounds %"struct.std::array", %"struct.std::array"* undef, i…
117 store i8 %conv.5.i.i, i8* %arrayidx.i.i7.5.i.i, align 1
[all …]
/external/tensorflow/tensorflow/core/util/
Dtensor_slice_util.h72 for (Index i7 = 0; i7 < len[7]; i7++) {
75 d_start[6] + i6, d_start[7] + i7) =
78 s_start[6] + i6, s_start[7] + i7);
109 for (Index i7 = 0; i7 < len[7]; i7++) {
112 d_start[6] + i6, d_start[7] + i7) =
116 s_start[6] + i6, s_start[7] + i7));
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dfunnel-shift.ll65 declare i7 @llvm.fshl.i7(i7, i7, i7)
66 define i7 @fshl_i7_const_fold() {
71 %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
72 ret i7 %f
197 declare i7 @llvm.fshr.i7(i7, i7, i7)
198 define i7 @fshr_i7_const_fold() {
203 %f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
204 ret i7 %f
/external/clang/test/CodeGen/
Darm64-arguments.c297 int f38_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f38_stack() argument
308 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f38_stack()
350 int f39_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f39_stack() argument
361 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f39_stack()
405 int f40_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f40_stack() argument
416 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f40_stack()
460 int f41_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f41_stack() argument
471 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f41_stack()
517 int f42_stack(int i, int i2, int i3, int i4, int i5, int i6, int i7, int i8, in f42_stack() argument
524 return s1.i + s2.i + i + i2 + i3 + i4 + i5 + i6 + i7 + i8 + i9 + s1.s + s2.s; in f42_stack()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dmulwide.ll72 define i64 @mulwideu7(i7 %a, i7 %b) {
75 %val0 = zext i7 %a to i64
76 %val1 = zext i7 %b to i64
83 define i64 @mulwides7(i7 %a, i7 %b) {
86 %val0 = sext i7 %a to i64
87 %val1 = sext i7 %b to i64
/external/llvm/test/CodeGen/NVPTX/
Dmulwide.ll72 define i64 @mulwideu7(i7 %a, i7 %b) {
75 %val0 = zext i7 %a to i64
76 %val1 = zext i7 %b to i64
83 define i64 @mulwides7(i7 %a, i7 %b) {
86 %val0 = sext i7 %a to i64
87 %val1 = sext i7 %b to i64
/external/llvm/test/CodeGen/SPARC/
D64spill.ll13 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
24 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
35 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
47 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
58 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
69 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
80 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
91 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
102 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…
113 …%0 = tail call i64 asm sideeffect "#$0 $1", "=r,r,~{i0},~{i1},~{i2},~{i3},~{i4},~{i5},~{i6},~{i7},…

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