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Searched refs:imm2 (Results 1 – 25 of 35) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86GenFastISel.inc3732 …T_v2f64_rri(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t imm2) {
3736 …rn FastEmitInst_rri(X86::VCMPPDrri, X86::VR128RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill, imm2);
3739 …urn FastEmitInst_rri(X86::CMPPDrri, X86::VR128RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill, imm2);
3744 …T_v4f64_rri(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t imm2) {
3748 …n FastEmitInst_rri(X86::VCMPPDYrri, X86::VR256RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill, imm2);
3753 …rri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t imm2) {
3755 …VT::v2f64: return FastEmit_X86ISD_CMPPD_MVT_v2f64_rri(RetVT, Op0, Op0IsKill, Op1, Op1IsKill, imm2);
3756 …VT::v4f64: return FastEmit_X86ISD_CMPPD_MVT_v4f64_rri(RetVT, Op0, Op0IsKill, Op1, Op1IsKill, imm2);
3763 …T_v4f32_rri(MVT RetVT, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t imm2) {
3767 …rn FastEmitInst_rri(X86::VCMPPSrri, X86::VR128RegisterClass, Op0, Op0IsKill, Op1, Op1IsKill, imm2);
[all …]
/external/u-boot/post/lib_powerpc/
Dcpu_asm.h162 #define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ argument
168 ((imm2) << 1))
169 #define ASM_113(opcode, rd, rs, imm1, imm2, imm3) \ argument
174 ((imm2) << 6) + \
/external/v8/src/arm64/
Dassembler-arm64-inl.h1082 Instr Assembler::ImmBarrierDomain(int imm2) {
1083 DCHECK(is_uint2(imm2));
1084 return imm2 << ImmBarrierDomain_offset;
1088 Instr Assembler::ImmBarrierType(int imm2) {
1089 DCHECK(is_uint2(imm2));
1090 return imm2 << ImmBarrierType_offset;
/external/syzkaller/sys/linux/
Dbpf.txt232 imm2 int32
244 imm2 const[0, int32]
/external/v8/src/wasm/
Dwasm-module-builder.cc97 const byte imm2) { in EmitWithU8U8() argument
100 body_.write_u8(imm2); in EmitWithU8U8()
Dwasm-module-builder.h171 void EmitWithU8U8(WasmOpcode opcode, const byte imm1, const byte imm2);
/external/llvm/lib/Target/Mips/
DMips32r6InstrFormats.td493 bits<2> imm2;
502 let Inst{7-6} = imm2;
DMicroMips32r6InstrFormats.td412 bits<2> imm2;
420 let Inst{10-9} = imm2;
DMips32r6InstrInfo.td671 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
672 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips32r6InstrFormats.td508 bits<2> imm2;
517 let Inst{7-6} = imm2;
DMicroMips32r6InstrFormats.td362 bits<2> imm2;
370 let Inst{10-9} = imm2;
DMips32r6InstrInfo.td750 dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2);
751 string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $imm2");
/external/pcre/dist2/src/sljit/
DsljitNativeARM_32.c1194 sljit_uw imm2; in generate_int() local
1237 imm2 = SRC2_IMM | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8); in generate_int()
1260 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1290 imm2 = SRC2_IMM | (imm >> 24) | ((rol & 0xf) << 8); in generate_int()
1296 FAIL_IF(push_inst(compiler, (positive ? ORR : BIC) | RD(reg) | RN(reg) | imm2)); in generate_int()
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_peephole.cpp742 ImmediateValue &imm2) in expr() argument
744 struct Storage *const a = &imm0.reg, *const b = &imm1.reg, *const c = &imm2.reg; in expr()
841 const int s, ImmediateValue& imm2) in tryCollapseChainedMULs() argument
847 float f = imm2.reg.data.f32 * exp2f(mul2->postFactor); in tryCollapseChainedMULs()
905 ConstantFolding::opnd3(Instruction *i, ImmediateValue &imm2) in opnd3() argument
910 if (imm2.isInteger(0)) { in opnd3()
918 if (imm2.isInteger(0)) { in opnd3()
/external/vixl/src/aarch64/
Dassembler-aarch64.h3792 static Instr ImmBarrierDomain(int imm2) { in ImmBarrierDomain() argument
3793 VIXL_ASSERT(IsUint2(imm2)); in ImmBarrierDomain()
3794 return imm2 << ImmBarrierDomain_offset; in ImmBarrierDomain()
3797 static Instr ImmBarrierType(int imm2) { in ImmBarrierType() argument
3798 VIXL_ASSERT(IsUint2(imm2)); in ImmBarrierType()
3799 return imm2 << ImmBarrierType_offset; in ImmBarrierType()
/external/vixl/test/aarch64/
Dtest-simulator-aarch64.cc217 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2791 for (unsigned imm2 = 0; imm2 < inputs_imm2_length; imm2++) { in TestOpImmOpImmNEON() local
2800 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2827 (imm2 * vd_lane_count) + lane; in TestOpImmOpImmNEON()
2832 unsigned input_index_imm2 = imm2; in TestOpImmOpImmNEON()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_shader_tgsi_mem.c1014 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0); in fix_resinfo() local
1016 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, ""); in fix_resinfo()
1019 out = LLVMBuildInsertElement(builder, out, z, imm2, ""); in fix_resinfo()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td208 // t2addrmode_so_reg := reg + (reg << imm2)
514 let Inst{7-6} = 0b00; // imm2
592 let Inst{7-6} = 0b00; // imm2
681 let Inst{7-6} = 0b00; // imm2
722 let Inst{7-6} = 0b00; // imm2
845 let Inst{7-6} = 0b00; // imm2
1512 let Inst{5-4} = addr{1-0}; // imm2
2056 let Inst{7-6} = 0b00; // imm2 = '00'
2079 let Inst{7-6} = 0b00; // imm2 = '00'
2274 let Inst{7-6} = 0b00; // imm2
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td265 // t2addrmode_so_reg := reg + (reg << imm2)
602 let Inst{7-6} = 0b00; // imm2
686 let Inst{7-6} = 0b00; // imm2
807 let Inst{7-6} = 0b00; // imm2
849 let Inst{7-6} = 0b00; // imm2
947 let Inst{7-6} = 0b00; // imm2
1670 let Inst{5-4} = addr{1-0}; // imm2
2261 let Inst{7-6} = 0b00; // imm2 = '00'
2284 let Inst{7-6} = 0b00; // imm2 = '00'
2489 let Inst{7-6} = 0b00; // imm2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td268 // t2addrmode_so_reg := reg + (reg << imm2)
608 let Inst{7-6} = 0b00; // imm2
692 let Inst{7-6} = 0b00; // imm2
813 let Inst{7-6} = 0b00; // imm2
855 let Inst{7-6} = 0b00; // imm2
953 let Inst{7-6} = 0b00; // imm2
1676 let Inst{5-4} = addr{1-0}; // imm2
2559 let Inst{7-6} = 0b00; // imm2
3084 let Inst{7-6} = 0b00; // imm2
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1573 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 in processInstruction() local
1574 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1795 MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32 in processInstruction() local
1796 Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2); in processInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DREADME-SSE.txt467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
/external/llvm/lib/Target/X86/
DREADME-SSE.txt467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
/external/v8/src/compiler/arm64/
Dcode-generator-arm64.cc2111 int64_t imm2 = in AssembleArchInstruction() local
2115 __ Movi(temp, imm2, imm1); in AssembleArchInstruction()

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