Home
last modified time | relevance | path

Searched refs:input_rate (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dclock.h56 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) in clk_get_divisor() argument
60 clk_div = input_rate / output_rate; in clk_get_divisor()
/external/u-boot/drivers/spi/
Drk_spi.c48 uint input_rate; member
83 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk()
95 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
264 priv->input_rate = ret; in rockchip_spi_probe()
265 debug("%s: rate = %u\n", __func__, priv->input_rate); in rockchip_spi_probe()
/external/u-boot/drivers/clk/rockchip/
Dclk_rk3036.c26 #define RATE_TO_DIV(input_rate, output_rate) \ argument
27 ((input_rate) / (output_rate) - 1);
29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
Dclk_rk3328.c28 #define RATE_TO_DIV(input_rate, output_rate) \ argument
29 ((input_rate) / (output_rate) - 1);
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
Dclk_rv1108.c27 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
Dclk_rk3399.c40 #define RATE_TO_DIV(input_rate, output_rate) \ argument
41 ((input_rate) / (output_rate) - 1);
42 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
Dclk_rk322x.c26 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
Dclk_rk3128.c27 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
Dclk_rk3188.c71 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
Dclk_rk3368.c41 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
Dclk_rk3288.c130 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
/external/u-boot/arch/arm/mach-exynos/
Dclock.c1395 unsigned int fine_scalar_bits, unsigned int input_rate, in clock_calc_best_scalar() argument
1404 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate, in clock_calc_best_scalar()
1412 if (input_rate == 0 || target_rate == 0) in clock_calc_best_scalar()
1415 if (target_rate >= input_rate) in clock_calc_best_scalar()
1420 max(min(input_rate / i / target_rate, cap), 1U); in clock_calc_best_scalar()
1421 const unsigned int effective_rate = input_rate / i / in clock_calc_best_scalar()
/external/u-boot/drivers/clk/aspeed/
Dclk_ast2500.c178 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2500_calc_clock_config() argument
185 const ulong input_rate_khz = input_rate / 1000; in ast2500_calc_clock_config()
/external/webrtc/webrtc/modules/audio_processing/test/
Daudio_processing_unittest.cc258 int input_rate, in OutputFilePath() argument
268 ss << name << "_i" << num_input_channels << "_" << input_rate / 1000 << "_ir" in OutputFilePath()
2383 static void ProcessFormat(int input_rate, in ProcessFormat() argument
2398 {{input_rate, num_input_channels}, in ProcessFormat()
2406 FILE* near_file = fopen(ResourceFilePath("near", input_rate).c_str(), "rb"); in ProcessFormat()
2408 fopen(OutputFilePath(output_file_prefix, input_rate, output_rate, in ProcessFormat()
2415 fopen(OutputFilePath(output_file_prefix, input_rate, output_rate, in ProcessFormat()
2426 ChannelBuffer<float> fwd_cb(SamplesFromRate(input_rate), in ProcessFormat()
2456 input_rate, in ProcessFormat()