/external/swiftshader/third_party/LLVM/include/llvm/MC/ |
D | MCInstrDesc.h | 84 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef() function
|
/external/llvm/include/llvm/MC/ |
D | MCInstrDesc.h | 85 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef() function
|
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
D | MCInstrDesc.h | 96 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef() function
|
/external/llvm/lib/CodeGen/ |
D | TargetSchedule.cpp | 212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
|
D | MachineVerifier.cpp | 900 else if (!MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand() 910 if (MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
|
D | MachineInstr.cpp | 1802 if (MCOI.isOptionalDef()) in print()
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
D | TargetSchedule.cpp | 243 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
|
D | MachineVerifier.cpp | 1106 else if (!MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand() 1116 if (MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
|
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMCodeEmitter.cpp | 1333 !MCID.OpInfo[OpIdx].isOptionalDef()) in emitMulFrmInstruction() 1370 !MCID.OpInfo[OpIdx].isOptionalDef()) in emitExtendInstruction() 1399 MCID.OpInfo[OpIdx].isOptionalDef()) { in emitMiscArithInstruction() 1613 MCID.OpInfo[OpIdx].isOptionalDef()) { in emitVFPArithInstruction()
|
D | Thumb2SizeReduction.cpp | 657 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr() 747 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceToNarrow()
|
D | ARMISelLowering.cpp | 6334 if (!MCID.hasOptionalDef() || !MCID.OpInfo[ccOutIdx].isOptionalDef()) { in AdjustInstrPostInstrSelection()
|
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/ |
D | Assembler.cpp | 100 if (IsDef && !OpInfo.isOptionalDef()) in fillMachineFunction()
|
/external/llvm/lib/Target/ARM/ |
D | Thumb2SizeReduction.cpp | 795 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr() 890 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceToNarrow()
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | Thumb2SizeReduction.cpp | 821 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr() 913 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceToNarrow()
|
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 200 if (II.OpInfo[i].isOptionalDef()) { in CreateVirtualRegisters() 287 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 236 if (II.OpInfo[i].isOptionalDef()) { in CreateVirtualRegisters() 326 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 237 if (II.OpInfo[i].isOptionalDef()) { in CreateVirtualRegisters() 326 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
|
D | ScheduleDAGRRList.cpp | 1407 if (MCID.OpInfo[i].isOptionalDef()) { in DelayForLiveRegsBottomUp()
|
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
D | MachineVerifier.cpp | 610 if (MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
|
D | MachineInstr.cpp | 1449 if (MCOI.isOptionalDef()) in print()
|
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
|
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 4370 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; in checkTargetMatchPredicate()
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 562 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
|
/external/llvm/lib/Target/ARM/Disassembler/ |
D | ARMDisassembler.cpp | 579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
|
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 9039 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; in checkTargetMatchPredicate()
|