| /external/gemmlowp/meta/generators/ |
| D | qnt_Nx8_neon.py | 89 for lane in lanes:
90 emitter.EmitVAdd('i32', lane[0], lane[0], lane[1])
92 for lane in lanes:
93 emitter.EmitVMul('i32', lane[0], lane[0], multiplicative_offset)
95 for lane in lanes:
96 emitter.EmitVAdd('i32', lane[0], lane[0], rounding_offset)
98 for lane in lanes:
99 emitter.EmitVShl('s32', lane[0], lane[0], shift)
101 for lane in lanes:
102 emitter.EmitVQmovn('s32', lane[2], lane[0])
[all …]
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| D | zip_Nx8_neon.py | 65 for lane in lanes:
66 emitter.EmitVMov('i16', lane.aggregator, emitter.ImmediateConstant(0))
74 for lane in lanes:
76 '1.8', lane.load,
77 emitter.DereferenceIncrement(lane.input_address, alignment))
80 for lane in lanes:
81 emitter.EmitVAddw('u8', lane.aggregator, lane.aggregator, lane.load)
82 store_registers.append(lane.load)
95 for lane in lanes:
96 emitter.EmitVMov('i8', lane.load, emitter.ImmediateConstant(0))
[all …]
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| /external/u-boot/drivers/phy/marvell/ |
| D | comphy_a3700.c | 339 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane) in usb3_reg_set16() argument
349 if (lane == 2) in usb3_reg_set16()
361 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) in comphy_usb3_power_up() argument
381 usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane); in comphy_usb3_power_up()
395 | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane); in comphy_usb3_power_up()
398 usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane); in comphy_usb3_power_up()
404 usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane); in comphy_usb3_power_up()
408 usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane); in comphy_usb3_power_up()
411 usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane); in comphy_usb3_power_up()
417 usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane); in comphy_usb3_power_up()
[all …]
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| D | comphy_mux.c | 23 int lane, opt, valid; in comphy_mux_check_config() local
27 for (lane = 0; lane < comphy_max_lanes; in comphy_mux_check_config()
28 lane++, comphy_map_data++, mux_data++) { in comphy_mux_check_config()
43 lane, comphy_map_data->type); in comphy_mux_check_config()
44 debug("set lane %d as type %d\n", lane, in comphy_mux_check_config()
49 lane, comphy_map_data->type); in comphy_mux_check_config()
57 u32 type, int lane) in comphy_mux_get_mux_value() argument
84 u32 lane, value, offset, mask; in comphy_mux_reg_write() local
88 for (lane = 0; lane < comphy_max_lanes; in comphy_mux_reg_write()
89 lane++, comphy_map_data++, mux_data++) { in comphy_mux_reg_write()
[all …]
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| D | comphy_core.c | 54 u32 lane; in comphy_print() local
56 for (lane = 0; lane < chip_cfg->comphy_lanes_count; in comphy_print()
57 lane++, comphy_map_data++) { in comphy_print()
59 printf("Comphy-%d: %-13s\n", lane, in comphy_print()
62 printf("Comphy-%d: %-13s %-10s\n", lane, in comphy_print()
76 int lane; in comphy_probe() local
122 lane = 0; in comphy_probe()
128 comphy_map_data[lane].speed = fdtdec_get_int( in comphy_probe()
130 comphy_map_data[lane].type = fdtdec_get_int( in comphy_probe()
132 comphy_map_data[lane].invert = fdtdec_get_int( in comphy_probe()
[all …]
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| D | comphy_cp110.c | 19 #define SD_ADDR(base, lane) (base + 0x1000 * lane) argument
20 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800) argument
21 #define COMPHY_ADDR(base, lane) (base + 0x28 * lane) argument
86 static int comphy_pcie_power_up(u32 lane, u32 pcie_width, bool clk_src, in comphy_pcie_power_up() argument
91 void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane); in comphy_pcie_power_up()
92 void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane); in comphy_pcie_power_up()
112 if (lane == 0) { in comphy_pcie_power_up()
129 if (pcie_clk && clk_src && (lane == 5)) { in comphy_pcie_power_up()
191 if (lane == 0) { in comphy_pcie_power_up()
194 } else if (lane == (pcie_width - 1)) { in comphy_pcie_power_up()
[all …]
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| /external/u-boot/arch/powerpc/cpu/mpc85xx/ |
| D | fsl_corenet_serdes.c | 95 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
97 return lanes[lane].idx; in serdes_get_lane_idx()
100 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
102 return lanes[lane].bank; in serdes_get_bank_by_lane()
105 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
110 int bank = lanes[lane].bank; in serdes_lane_enabled()
111 int word = lanes[lane].lpd / 32; in serdes_lane_enabled()
112 int bit = lanes[lane].lpd % 32; in serdes_lane_enabled()
124 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); in serdes_lane_enabled()
189 int lane; in serdes_get_bank_by_device() local
[all …]
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| D | p1010_serdes.c | 57 int lane; in fsl_serdes_init() local
69 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
70 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
82 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
83 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
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| D | mpc8544_serdes.c | 58 int lane; in fsl_serdes_init() local
70 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
71 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
83 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
84 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
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| D | p1022_serdes.c | 96 int lane; in fsl_serdes_init() local
108 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
109 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
121 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
122 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
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| /external/u-boot/board/highbank/ |
| D | ahci.c | 81 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) in cphy_spread_spectrum_override() argument
84 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
86 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
89 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
93 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
96 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
102 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
109 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
111 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
114 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
[all …]
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| /external/u-boot/board/freescale/p2041rdb/ |
| D | eth.c | 92 int lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + port); in board_ft_fman_fixup_port() local
94 if (lane < 0) in board_ft_fman_fixup_port()
96 slot = lane_to_slot[lane]; in board_ft_fman_fixup_port()
112 int lane = serdes_get_first_lane(XAUI_FM1); in board_ft_fman_fixup_port() local
113 if (lane >= 0) { in board_ft_fman_fixup_port()
115 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); in board_ft_fman_fixup_port()
128 int lane; in board_eth_init() local
163 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); in board_eth_init()
164 if (lane < 0) in board_eth_init()
166 slot = lane_to_slot[lane]; in board_eth_init()
[all …]
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| /external/u-boot/board/freescale/corenet_ds/ |
| D | eth_superhydra.c | 217 int lane, slot, phy; in board_ft_fman_fixup_port() local
224 lane = serdes_get_first_lane(device); in board_ft_fman_fixup_port()
225 slot = lane_to_slot[lane]; in board_ft_fman_fixup_port()
299 int lane, slot; in fdt_fixup_board_enet() local
306 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); in fdt_fixup_board_enet()
307 if (lane >= 0) { in fdt_fixup_board_enet()
310 slot = lane_to_slot[lane]; in fdt_fixup_board_enet()
326 lane = serdes_get_first_lane(XAUI_FM1); in fdt_fixup_board_enet()
327 if (lane >= 0) { in fdt_fixup_board_enet()
330 slot = lane_to_slot[lane]; in fdt_fixup_board_enet()
[all …]
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| D | eth_hydra.c | 245 int lane = serdes_get_first_lane(XAUI_FM1); in board_ft_fman_fixup_port() local
246 if (lane >= 0) { in board_ft_fman_fixup_port()
248 sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]); in board_ft_fman_fixup_port()
336 int lane; in fdt_fixup_board_enet() local
343 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); in fdt_fixup_board_enet()
344 if (lane >= 0) { in fdt_fixup_board_enet()
359 lane = serdes_get_first_lane(XAUI_FM1); in fdt_fixup_board_enet()
360 if (lane >= 0) in fdt_fixup_board_enet()
371 int lane; in board_eth_init() local
416 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); in board_eth_init()
[all …]
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| D | eth_p4080.c | 341 int idx = i - FM1_DTSEC1, lane, slot; in board_eth_init() local
344 lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); in board_eth_init()
345 if (lane < 0) in board_eth_init()
347 slot = lane_to_slot[lane]; in board_eth_init()
381 int idx = i - FM1_10GEC1, lane, slot; in board_eth_init() local
384 lane = serdes_get_first_lane(XAUI_FM1 + idx); in board_eth_init()
385 if (lane < 0) in board_eth_init()
387 slot = lane_to_slot[lane]; in board_eth_init()
408 int idx = i - FM2_DTSEC1, lane, slot; in board_eth_init() local
411 lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); in board_eth_init()
[all …]
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| /external/python/cpython3/Modules/_sha3/kcp/ |
| D | KeccakP-1600-opt64.c | 98 UINT64 lane; in KeccakP1600_AddBytesInLane() local
102 lane = data[0]; in KeccakP1600_AddBytesInLane()
104 lane = 0; in KeccakP1600_AddBytesInLane()
105 memcpy(&lane, data, length); in KeccakP1600_AddBytesInLane()
107 lane <<= offset*8; in KeccakP1600_AddBytesInLane()
109 UINT64 lane = 0; in KeccakP1600_AddBytesInLane()
112 lane |= ((UINT64)data[i]) << ((i+offset)*8); in KeccakP1600_AddBytesInLane()
114 ((UINT64*)state)[lanePosition] ^= lane; in KeccakP1600_AddBytesInLane()
164 UINT64 lane = (UINT64)curData[0] in KeccakP1600_AddLanes()
172 ((UINT64*)state)[i] ^= lane; in KeccakP1600_AddLanes()
[all …]
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| /external/u-boot/board/freescale/t1040qds/ |
| D | eth.c | 299 int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1 in board_ft_fman_fixup_port() local
302 if (lane < 0) in board_ft_fman_fixup_port()
304 slot = lane_to_slot[lane]; in board_ft_fman_fixup_port()
317 int i, lane, idx; in fdt_fixup_board_enet() local
323 lane = serdes_get_first_lane(FSL_SRDS_1, in fdt_fixup_board_enet()
325 if (lane < 0) in fdt_fixup_board_enet()
369 int lane, idx, slot; in t1040_handle_phy_interface_sgmii() local
371 lane = serdes_get_first_lane(FSL_SRDS_1, in t1040_handle_phy_interface_sgmii()
374 if (lane < 0) in t1040_handle_phy_interface_sgmii()
376 slot = lane_to_slot[lane]; in t1040_handle_phy_interface_sgmii()
[all …]
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| /external/u-boot/arch/arm/mach-tegra/ |
| D | xusb-padctl-common.c | 129 const struct tegra_xusb_padctl_lane *lane, in tegra_xusb_padctl_lane_find_function() argument
139 for (i = 0; i < lane->num_funcs; i++) in tegra_xusb_padctl_lane_find_function()
140 if (lane->funcs[i] == func) in tegra_xusb_padctl_lane_find_function()
153 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_group_apply() local
157 lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); in tegra_xusb_padctl_group_apply()
158 if (!lane) { in tegra_xusb_padctl_group_apply()
163 func = tegra_xusb_padctl_lane_find_function(padctl, lane, in tegra_xusb_padctl_group_apply()
167 group->func, lane->name, func); in tegra_xusb_padctl_group_apply()
171 value = padctl_readl(padctl, lane->offset); in tegra_xusb_padctl_group_apply()
174 value &= ~(lane->mask << lane->shift); in tegra_xusb_padctl_group_apply()
[all …]
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| /external/u-boot/arch/powerpc/cpu/mpc86xx/ |
| D | mpc8610_serdes.c | 54 int lane; in fsl_serdes_init() local
66 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
67 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
79 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
80 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
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| D | mpc8641_serdes.c | 63 int lane; in fsl_serdes_init() local
75 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
76 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
88 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
89 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane]; in fsl_serdes_init()
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| /external/u-boot/drivers/soc/keystone/ |
| D | keystone_serdes.c | 46 struct serdes_cfg lane[SERDES_LANE_CFG_NUM]; member
88 .lane = {
117 u32 size, u32 lane) in ks2_serdes_lane_config() argument
122 ks2_serdes_rmw(base + cfg_lane[i].ofs + SERDES_LANE_REGS(lane), in ks2_serdes_lane_config()
134 ks2_serdes_lane_config(base, cfg->lane, SERDES_LANE_CFG_NUM, i); in ks2_serdes_init_cfg()
160 static void ks2_serdes_lane_reset(u32 base, u32 reset, u32 lane) in ks2_serdes_lane_reset() argument
163 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), in ks2_serdes_lane_reset()
166 ks2_serdes_rmw(base + SERDES_LANE_REG_028(lane), in ks2_serdes_lane_reset()
171 struct ks2_serdes *serdes, u32 lane) in ks2_serdes_lane_enable() argument
174 ks2_serdes_lane_reset(base, 0, lane); in ks2_serdes_lane_enable()
[all …]
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| /external/u-boot/drivers/video/rockchip/ |
| D | rk_edp.c | 353 static u8 edp_get_lane_status(const u8 *link_status, int lane) in edp_get_lane_status() argument
355 int i = DPCD_LANE0_1_STATUS + (lane >> 1); in edp_get_lane_status()
356 int s = (lane & 1) * 4; in edp_get_lane_status()
364 int lane; in rk_edp_clock_recovery() local
367 for (lane = 0; lane < lane_count; lane++) { in rk_edp_clock_recovery()
368 lane_status = edp_get_lane_status(link_status, lane); in rk_edp_clock_recovery()
380 int lane; in rk_edp_channel_eq() local
386 for (lane = 0; lane < lane_count; lane++) { in rk_edp_channel_eq()
387 lane_status = edp_get_lane_status(link_status, lane); in rk_edp_channel_eq()
395 static uint rk_edp_get_adjust_request_voltage(const u8 *link_status, int lane) in rk_edp_get_adjust_request_voltage() argument
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 545 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
550 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
553 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
558 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
561 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
566 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
568 // VLD1LN : Vector Load (single element to one lane)
572 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
573 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
577 imm:$lane))]> {
[all …]
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| /external/u-boot/board/freescale/t4qds/ |
| D | eth.c | 489 int i, idx, lane, slot, interface; in board_eth_init() local
606 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
609 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
611 if (lane < 0) in board_eth_init()
613 slot = lane_to_slot_fsm1[lane]; in board_eth_init()
617 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
619 if (lane < 0) in board_eth_init()
621 slot = lane_to_slot_fsm1[lane]; in board_eth_init()
663 lane = serdes_get_first_lane(FSL_SRDS_1, in board_eth_init()
665 if (lane < 0) in board_eth_init()
[all …]
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| /external/neon_2_sse/ |
| D | NEON_2_SSE.h | 1250 …ansfersize(1) uint8_t const * ptr, uint8x16_t vec, __constrange(0,15) int lane); //VLD1.8 {d0[0]},…
1251 …ansfersize(1) uint16_t const * ptr, uint16x8_t vec, __constrange(0,7) int lane); // VLD1.16 {d0[0]…
1252 …ansfersize(1) uint32_t const * ptr, uint32x4_t vec, __constrange(0,3) int lane); // VLD1.32 {d0[0]…
1253 …ansfersize(1) uint64_t const * ptr, uint64x2_t vec, __constrange(0,1) int lane); // VLD1.64 {d0}, …
1254 …transfersize(1) int8_t const * ptr, int8x16_t vec, __constrange(0,15) int lane); //VLD1.8 {d0[0]},…
1255 …transfersize(1) int16_t const * ptr, int16x8_t vec, __constrange(0,7) int lane); //VLD1.16 {d0[0]}…
1256 …transfersize(1) int32_t const * ptr, int32x4_t vec, __constrange(0,3) int lane); //VLD1.32 {d0[0]}…
1257 …ransfersize(1) __fp16 const * ptr, float16x8_t vec, __constrange(0,7) int lane); //VLD1.16 {d0[0]}…
1258 …sfersize(1) float32_t const * ptr, float32x4_t vec, __constrange(0,3) int lane); // VLD1.32 {d0[0]…
1259 …transfersize(1) int64_t const * ptr, int64x2_t vec, __constrange(0,1) int lane); //VLD1.64 {d0}, […
[all …]
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