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Searched refs:lane_num (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/arch/arm/mach-mvebu/serdes/a38x/
Dhigh_speed_env_spec-38x.c81 int hws_is_serdes_active(u8 lane_num) in hws_is_serdes_active() argument
86 if (lane_num > 6) in hws_is_serdes_active()
90 if (sys_env_device_id_get() == MV_6810 && lane_num == 4) { in hws_is_serdes_active()
100 if (sys_env_device_id_get() == MV_6810 && lane_num == 5) in hws_is_serdes_active()
103 if (lane_num >= hws_serdes_get_max_lane()) in hws_is_serdes_active()
Dhigh_speed_env_spec.c1365 u32 lane_num; in print_topology_details() local
1371 for (lane_num = 0; lane_num < count; lane_num++) { in print_topology_details()
1372 if (serdes_map[lane_num].serdes_type == DEFAULT_SERDES) in print_topology_details()
1375 DEBUG_INIT_D(hws_get_physical_serdes_num(lane_num), 1); in print_topology_details()
1377 DEBUG_INIT_D(serdes_map[lane_num].serdes_speed, 2); in print_topology_details()
1380 serdes_type_to_string[serdes_map[lane_num]. in print_topology_details()
Dhigh_speed_env_spec.h248 int hws_is_serdes_active(u8 lane_num);
/external/u-boot/drivers/video/exynos/
Dexynos_dp.c416 unsigned char lane_num, unsigned char *sw, unsigned char *em) in exynos_dp_read_dpcd_adj_req() argument
424 dpcd_addr = DPCD_ADJUST_REQUEST_LANE0_1 + (lane_num / 2); in exynos_dp_read_dpcd_adj_req()
432 *sw = ((buf >> shift_val[lane_num]) & 0x03); in exynos_dp_read_dpcd_adj_req()
433 *em = ((buf >> shift_val[lane_num]) & 0x0c) >> 2; in exynos_dp_read_dpcd_adj_req()
/external/tensorflow/tensorflow/lite/kernels/internal/optimized/
Ddepthwiseconv_uint8_3x3_filter.h42 #define vst1_lane_8x4(dst, reg, lane_num) \ argument
44 vst1_lane_u32(reinterpret_cast<uint32_t*>(dst), reg, lane_num)
45 #define vst1q_lane_8x4(dst, reg, lane_num) \ argument
47 vst1q_lane_u32(reinterpret_cast<uint32_t*>(dst), reg, lane_num)
49 #define vld1q_lane_s8x8(src, reg, lane_num) \ argument
50 vld1q_lane_u64(reinterpret_cast<const uint64_t*>(src), reg, lane_num)
51 #define vld1_lane_8x4(src, reg, lane_num) \ argument
52 vld1_lane_s32(reinterpret_cast<const int32*>(src), reg, lane_num)
53 #define vld1q_lane_8x4(src, reg, lane_num) \ argument
54 vld1q_lane_s32(reinterpret_cast<const int32*>(src), reg, lane_num)
Ddepthwiseconv_uint8_transitional.h44 #define vst1_lane_8x4(dst, reg, lane_num) \ argument
46 vst1_lane_u32(reinterpret_cast<uint32_t*>(dst), reg, lane_num)
47 #define vst1q_lane_8x4(dst, reg, lane_num) \ argument
49 vst1q_lane_u32(reinterpret_cast<uint32_t*>(dst), reg, lane_num)
51 #define vld1q_lane_s8x8(src, reg, lane_num) \ argument
52 vld1q_lane_u64(reinterpret_cast<const uint64_t*>(src), reg, lane_num)
53 #define vld1_lane_8x4(src, reg, lane_num) \ argument
54 vld1_lane_s32(reinterpret_cast<const int32*>(src), reg, lane_num)
55 #define vld1q_lane_8x4(src, reg, lane_num) \ argument
56 vld1q_lane_s32(reinterpret_cast<const int32*>(src), reg, lane_num)