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Searched refs:load0 (Results 1 – 25 of 30) sorted by relevance

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/external/llvm/test/CodeGen/AMDGPU/
Dvselect.ll15 %load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0
17 %cmp = icmp sgt <2 x i32> %load0, %load1
18 %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0
57 %load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0
59 %cmp = icmp sgt <4 x i32> %load0, %load1
60 %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0
Dschedule-global-loads.ll15 %load0 = load i32, i32 addrspace(1)* %ptr, align 4
18 store i32 %load0, i32 addrspace(1)* %out0, align 4
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dvselect.ll17 %load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0
19 %cmp = icmp sgt <2 x i32> %load0, %load1
20 %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0
60 %load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0
62 %cmp = icmp sgt <4 x i32> %load0, %load1
63 %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0
Dtrunc-combine.ll30 %load0 = load i32, i32 addrspace(1)* undef
32 %insert.0 = insertelement <2 x i32> undef, i32 %load0, i32 0
47 %load0 = load float, float addrspace(1)* undef
49 %insert.0 = insertelement <2 x float> undef, float %load0, i32 0
Dcontrol-flow-fastregalloc.ll77 %load0 = load volatile i32, i32 addrspace(3)* undef
83 %val = add i32 %load0, %load1
152 %load0 = load volatile i32, i32 addrspace(3)* undef
158 %val = phi i32 [ %val.sub, %loop ], [ %load0, %entry ]
270 %load0 = load volatile i32, i32 addrspace(3)* undef
276 %val0 = add i32 %load0, %load1
281 %val1 = sub i32 %load0, %load2
Dglobal_smrd.ll94 %load0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4
95 %load1 = load i32, i32 addrspace(1)* %load0, align 4
113 %load0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4
114 %load1 = load i32, i32 addrspace(1)* %load0, align 4
Dschedule-global-loads.ll14 %load0 = load i32, i32 addrspace(1)* %ptr, align 4
17 store i32 %load0, i32 addrspace(1)* %out0, align 4
Dload-hi16.ll581 %load0 = load volatile i16, i16 addrspace(3)* %in
583 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
600 %load0 = load volatile i16, i16 addrspace(1)* %in
602 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
619 %load0 = load volatile i16, i16* %in
621 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
638 %load0 = load volatile i16, i16 addrspace(4)* %in
640 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
657 %load0 = load volatile i16, i16 addrspace(5)* %in
659 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
Dmultilevel-break.ll95 %load0 = load volatile i32, i32 addrspace(1)* undef, align 4
96 switch i32 %load0, label %bb9 [
Dllvm.amdgcn.implicitarg.ptr.ll187 %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
214 %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
Dfunction-returns.ll541 %load0 = load volatile i32, i32 addrspace(3)* undef
546 %insert.0 = insertelement <3 x i32> undef, i32 %load0, i32 0
560 %load0 = load volatile float, float addrspace(3)* undef
565 %insert.0 = insertelement <3 x float> undef, float %load0, i32 0
Dframe-index-elimination.ll121 %load0 = load i8, i8 addrspace(5)* %gep0
123 store volatile i8 %load0, i8 addrspace(3)* undef
Drewrite-out-arguments.ll522 ; CHECK-NEXT: %load0 = load volatile [15 x i32], [15 x i32] addrspace(1)* undef
524 ; CHECK-NEXT: %1 = insertvalue %num_regs_reach_limit_leftover undef, [15 x i32] %load0, 0
538 %load0 = load volatile [15 x i32], [15 x i32] addrspace(1)* undef
542 ret [15 x i32] %load0
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/AArch64/
Dext-trunc.ll41 %load0 = load i64, i64* %gep0
54 call void @foo(i64 %load0, i64 %load1, i64 %load2, i64 %load3)
93 %load0 = load i64, i64* %gep0
109 call void @foo(i64 %load0, i64 %load1, i64 %load2, i64 %load3)
/external/swiftshader/third_party/llvm-7.0/llvm/test/Instrumentation/DataFlowSanitizer/
Dload.ll6 define {} @load0({}* %p) {
7 ; COMBINE_PTR_LABEL: @"dfs$load0"
11 ; NO_COMBINE_PTR_LABEL: @"dfs$load0"
/external/llvm/test/Instrumentation/DataFlowSanitizer/
Dload.ll6 define {} @load0({}* %p) {
7 ; COMBINE_PTR_LABEL: @"dfs$load0"
11 ; NO_COMBINE_PTR_LABEL: @"dfs$load0"
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonShuffler.cpp302 unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0; in check() local
339 ++load0; in check()
376 ++load0; in check()
408 if ((load0 > 1 || store0 > 1) || (duplex > 1 || (duplex && memory))) { in check()
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonShuffler.cpp177 unsigned memory = 0, loads = 0, load0 = 0, stores = 0, store0 = 0, store1 = 0; in check() local
232 ++load0; in check()
268 if ((load0 > 1 || store0 > 1 || CVIloads > 1 || CVIstores > 1) || in check()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/EarlyCSE/
Dbasic.ll198 %load0 = load i32, i32* %P1
201 %sel = select i1 %B, i32 %load0, i32 %load1
Datomics.ll6 %load0 = load i32, i32* %P1
9 %sel = select i1 %B, i32 %load0, i32 %load1
/external/llvm/test/Transforms/EarlyCSE/
Dbasic.ll197 %load0 = load i32, i32* %P1
200 %sel = select i1 %B, i32 %load0, i32 %load1
Datomics.ll5 %load0 = load i32, i32* %P1
8 %sel = select i1 %B, i32 %load0, i32 %load1
/external/llvm/test/CodeGen/AArch64/
Df16-convert.ll3 define float @load0(i16* nocapture readonly %a) nounwind {
4 ; CHECK-LABEL: load0:
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Df16-convert.ll3 define float @load0(i16* nocapture readonly %a) nounwind {
4 ; CHECK-LABEL: load0:
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Darm-cgp-icmps.ll185 %load0 = load i16, i16* %gep0, align 2
187 %sub1 = sub i16 %load0, %sub0

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