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Searched refs:ls_hs_config (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_draw.c117 unsigned offchip_layout, hardware_lds_size, ls_hs_config; in si_emit_derived_tess_state() local
300 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) | in si_emit_derived_tess_state()
306 ls_hs_config); in si_emit_derived_tess_state()
309 ls_hs_config); in si_emit_derived_tess_state()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_pipe.h794 uint32_t ls_hs_config);
Dr600_state_common.c2098 uint32_t ls_hs_config = evergreen_get_ls_hs_config(rctx, info, in r600_draw_vbo() local
2101 evergreen_set_ls_hs_config(rctx, cs, ls_hs_config); in r600_draw_vbo()
Devergreen_state.c4476 uint32_t ls_hs_config) in evergreen_set_ls_hs_config() argument
4478 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config); in evergreen_set_ls_hs_config()
/external/mesa3d/src/amd/vulkan/
Dradv_private.h1179 uint32_t ls_hs_config; member
Dradv_cmd_buffer.c866 pipeline->graphics.tess.ls_hs_config); in radv_emit_tess_shaders()
869 pipeline->graphics.tess.ls_hs_config); in radv_emit_tess_shaders()
Dradv_pipeline.c1460 tess->ls_hs_config = S_028B58_NUM_PATCHES(num_patches) | in calculate_tess_state()