Searched refs:next_tx (Results 1 – 3 of 3) sorted by relevance
57 static int next_tx; variable141 fifo_tx[next_tx].len = length; in au1x00_send()142 fifo_tx[next_tx].addr = (virt_to_phys(packet))|TX_DMA_ENABLE; in au1x00_send()147 while(!(fifo_tx[next_tx].addr&TX_T_DONE)){ in au1x00_send()157 fifo_tx[next_tx].addr = 0; in au1x00_send()158 fifo_tx[next_tx].len = 0; in au1x00_send()161 res = fifo_tx[next_tx].status; in au1x00_send()163 next_tx++; in au1x00_send()164 if(next_tx>=NO_OF_FIFOS){ in au1x00_send()165 next_tx=0; in au1x00_send()[all …]
314 struct Teq1Frame *next_tx) { in teq1_rules() argument338 next_tx->header.PCB = S(RESYNC, REQUEST); in teq1_rules()362 next_tx->header.PCB = in teq1_rules()364 next_tx->header.LEN = 0; in teq1_rules()371 next_tx->header.PCB = in teq1_rules()373 teq1_fill_info_block(state, next_tx); /* Sets M-bit and LEN. */ in teq1_rules()385 next_tx->header.PCB = S(WTX, RESPONSE); in teq1_rules()386 next_tx->header.LEN = 1; in teq1_rules()387 next_tx->INF[0] = rx_frame->INF[0]; in teq1_rules()404 next_tx->header.PCB = S(IFS, RESPONSE); in teq1_rules()[all …]
123 struct Teq1Frame *next_tx);