| /external/u-boot/drivers/clk/at91/ |
| D | clk-plladiv.c | 43 ulong parent_rate; in at91_plladiv_clk_set_rate() local
50 parent_rate = clk_get_rate(&source); in at91_plladiv_clk_set_rate()
51 if ((parent_rate != rate) && ((parent_rate) / 2 != rate)) in at91_plladiv_clk_set_rate()
54 if (parent_rate != rate) { in at91_plladiv_clk_set_rate()
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| D | clk-generated.c | 82 ulong tmp_rate, best_rate = rate, parent_rate; in generic_clk_set_rate() local
95 parent_rate = clk_get_rate(&parent); in generic_clk_set_rate()
96 if (IS_ERR_VALUE(parent_rate)) in generic_clk_set_rate()
97 return parent_rate; in generic_clk_set_rate()
100 tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div); in generic_clk_set_rate()
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| /external/u-boot/arch/arm/mach-tegra/ |
| D | clock.c | 245 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate, in clk_get_divider() argument
248 u64 divider = parent_rate * 2; in clk_get_divider()
299 static unsigned long get_rate_from_divider(unsigned long parent_rate, in get_rate_from_divider() argument
304 rate = (u64)parent_rate * 2; in get_rate_from_divider()
313 unsigned parent_rate = pll_rate[parent]; in clock_get_periph_rate() local
324 return parent_rate; in clock_get_periph_rate()
352 return get_rate_from_divider(parent_rate, div); in clock_get_periph_rate()
368 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate, in find_best_divider() argument
377 unsigned divided_parent = parent_rate >> shift; in find_best_divider()
527 unsigned int __weak clk_m_get_rate(unsigned int parent_rate) in clk_m_get_rate() argument
[all …]
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| /external/u-boot/drivers/clk/ |
| D | clk_meson.c | 162 unsigned long parent_rate; in meson_clk81_get_rate() local
181 parent_rate = XTAL_RATE; in meson_clk81_get_rate()
186 parent_rate = meson_clk_get_rate_by_id(clk, parents[reg]); in meson_clk81_get_rate()
193 return parent_rate / reg; in meson_clk81_get_rate()
196 static long mpll_rate_from_params(unsigned long parent_rate, in mpll_rate_from_params() argument
205 return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); in mpll_rate_from_params()
234 unsigned long parent_rate; in meson_mpll_get_rate() local
253 parent_rate = meson_clk_get_rate_by_id(clk, CLKID_FIXED_PLL); in meson_mpll_get_rate()
254 if (IS_ERR_VALUE(parent_rate)) in meson_mpll_get_rate()
255 return parent_rate; in meson_mpll_get_rate()
[all …]
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| D | clk_pic32.c | 170 int parent_rate, int rate, int parent_id) in pic32_set_refclk() argument
181 if (parent_rate <= rate) { in pic32_set_refclk()
185 div = parent_rate / (rate << 1); in pic32_set_refclk()
186 frac = parent_rate; in pic32_set_refclk()
231 u32 rodiv, rotrim, rosel, v, parent_rate; in pic32_get_refclk() local
254 parent_rate = pic32_get_cpuclk(priv); in pic32_get_refclk()
257 parent_rate = pic32_get_pll_rate(priv); in pic32_get_refclk()
260 parent_rate = 0; in pic32_get_refclk()
270 rate64 = parent_rate; in pic32_get_refclk()
275 v = parent_rate / (rodiv << 1); in pic32_get_refclk()
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| D | clk-hsdk-cgu.c | 510 ulong parent_rate = pll_get(sclk); in idiv_get() local
520 return parent_rate / div_factor; in idiv_get()
614 ulong parent_rate = pll_get(sclk); in idiv_set() local
617 div_factor = parent_rate / rate; in idiv_set()
618 if (abs(rate - parent_rate / (div_factor + 1)) <= in idiv_set()
619 abs(rate - parent_rate / div_factor)) { in idiv_set()
625 rate, parent_rate, div_factor, CGU_IDIV_MASK); in idiv_set()
632 rate, parent_rate, div_factor); in idiv_set()
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| /external/u-boot/drivers/clk/uniphier/ |
| D | clk-uniphier-core.c | 183 unsigned long parent_rate; in __uniphier_clk_set_rate() local
207 parent_rate = __uniphier_clk_set_rate(priv, parent_data, rate, in __uniphier_clk_set_rate()
210 if (parent_rate <= rate && best_rate < parent_rate) { in __uniphier_clk_set_rate()
211 best_rate = parent_rate; in __uniphier_clk_set_rate()
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| /external/u-boot/drivers/video/ |
| D | ipu_common.c | 306 u64 parent_rate = (unsigned long long)clk->parent->rate * 16; in ipu_pixel_clk_round_rate() local
313 div = parent_rate; in ipu_pixel_clk_round_rate()
329 final_rate = parent_rate; in ipu_pixel_clk_round_rate()
337 u64 div, parent_rate; in ipu_pixel_clk_set_rate() local
340 parent_rate = (unsigned long long)clk->parent->rate * 16; in ipu_pixel_clk_set_rate()
341 div = parent_rate; in ipu_pixel_clk_set_rate()
363 do_div(parent_rate, div); in ipu_pixel_clk_set_rate()
365 clk->rate = parent_rate; in ipu_pixel_clk_set_rate()
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| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rk3368.c | 221 ulong parent_rate = parents[i].rate; in rk3368_mmc_find_best_rate_and_parent() local
222 u32 div = DIV_ROUND_UP(parent_rate, rate); in rk3368_mmc_find_best_rate_and_parent()
224 ulong new_rate = parent_rate / adj_div; in rk3368_mmc_find_best_rate_and_parent()
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| /external/u-boot/arch/arm/mach-imx/mx5/ |
| D | clock.c | 724 u32 parent_rate = get_emi_slow_clk(); in config_nfc_clk() local
729 div = parent_rate / nfc_clk; in config_nfc_clk()
732 if (parent_rate / div > NFC_CLK_MAX) in config_nfc_clk()
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| /external/u-boot/arch/arm/include/asm/arch-tegra/ |
| D | clock.h | 47 unsigned int clk_m_get_rate(unsigned int parent_rate);
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| /external/u-boot/arch/arm/mach-tegra/tegra210/ |
| D | clock.c | 1033 unsigned int clk_m_get_rate(unsigned parent_rate) in clk_m_get_rate() argument
1041 return parent_rate / div; in clk_m_get_rate()
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