| /external/elfutils/tests/ |
| D | run-readelf-loc.sh | 71 [ 0] reg5
75 [ 0] reg5
112 [ 0] reg5
116 [ 0] reg5
151 [ 0] reg5
153 [ 0] reg5
188 [ 0] reg5
193 [ 0] reg5
208 [ 0] reg5
215 [ 0] reg5
[all …]
|
| D | run-varlocs.sh | 57 [400500,400504) {reg5}
63 [400510,40051c) {reg5}
65 [40052b,400531) {GNU_entry_value(1) {reg5}, stack_value}
78 [400400,400406) {reg5}
80 [40040a,40040b) {GNU_entry_value(1) {reg5}, stack_value}
92 [400510,400523) {reg5}
106 [400400,400408) {reg5}
108 [400421,400423) {GNU_entry_value(1) {reg5}, stack_value}
120 [400500,400503) {reg5}
122 [400500,400503) {GNU_implicit_pointer([4a],0) {reg5}}
[all …]
|
| D | run-dwarfcfi.sh | 43 reg5: same_value
60 reg5: undefined
77 reg5: undefined
94 reg5: undefined
111 reg5: same_value
128 reg5: undefined
|
| D | run-readelf-zdebug-rel.sh | 100 [ 0] reg5
133 [ 0] reg5
139 [ 0] reg5
|
| D | run-readelf-zdebug.sh | 52 [ 0] reg5
58 [ 0] reg5
|
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
51 DOTP_CONST_PAIR(reg5, reg3, cospi_12_64, cospi_20_64, reg5, reg3); in idct32x8_row_even_process_store()
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
68 DOTP_CONST_PAIR(reg2, reg5, cospi_22_64, cospi_10_64, reg2, reg5); in idct32x8_row_even_process_store()
75 reg2 = reg1 + reg5; in idct32x8_row_even_process_store()
76 reg1 = reg1 - reg5; in idct32x8_row_even_process_store()
77 reg5 = reg7 + reg3; in idct32x8_row_even_process_store()
84 reg4 = reg5 - vec1; in idct32x8_row_even_process_store()
[all …]
|
| D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa()
24 reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
48 DOTP_CONST_PAIR(reg5, reg11, cospi_22_64, cospi_10_64, reg5, reg11); in vpx_idct16_1d_rows_msa()
50 BUTTERFLY_4(loc0, loc1, reg11, reg5, reg13, reg3, reg11, reg5); in vpx_idct16_1d_rows_msa()
66 DOTP_CONST_PAIR((-reg5), (-reg11), cospi_8_64, cospi_24_64, reg5, reg11); in vpx_idct16_1d_rows_msa()
68 loc0 = reg9 + reg5; in vpx_idct16_1d_rows_msa()
69 reg5 = reg9 - reg5; in vpx_idct16_1d_rows_msa()
79 DOTP_CONST_PAIR(reg5, reg11, cospi_16_64, cospi_16_64, reg5, reg11); in vpx_idct16_1d_rows_msa()
[all …]
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| /external/u-boot/board/freescale/ls1043ardb/ |
| D | cpld.c | 32 u8 reg5 = (u8)(reg >> 1); in cpld_set_altbank() local
36 cpld_rev_bit(®5); in cpld_set_altbank()
40 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_altbank()
54 u8 reg5 = (u8)(reg >> 1); in cpld_set_defbank() local
57 cpld_rev_bit(®5); in cpld_set_defbank()
61 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_defbank()
72 u8 reg5 = (u8)(reg >> 1); in cpld_set_nand() local
75 cpld_rev_bit(®5); in cpld_set_nand()
79 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_nand()
88 u8 reg5 = (u8)(reg >> 1); in cpld_set_sd() local
[all …]
|
| /external/u-boot/board/freescale/ls1046ardb/ |
| D | cpld.c | 32 u8 reg5 = (u8)(reg >> 1); in cpld_set_altbank() local
36 cpld_rev_bit(®5); in cpld_set_altbank()
40 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_altbank()
54 u8 reg5 = (u8)(reg >> 1); in cpld_set_defbank() local
57 cpld_rev_bit(®5); in cpld_set_defbank()
61 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_defbank()
72 u8 reg5 = (u8)(reg >> 1); in cpld_set_sd() local
75 cpld_rev_bit(®5); in cpld_set_sd()
79 CPLD_WRITE(cfg_rcw_src1, reg5); in cpld_set_sd()
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 51 ; ARMv7: movw r[[reg5:[0-9]+]],
52 ; ARMv7: movt r[[reg5]],
53 ; ARMv7: add r[[reg5]], pc, r[[reg5]]
54 ; ARMv7: ldr r[[reg5]], [r[[reg5]]]
56 ; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
58 ; ARMv7-ELF: ldr r[[reg6:[0-9]+]], [pc, r[[reg5]]]
59 ; ARMv7-ELF: ldr r0, [r[[reg5]]]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 51 ; ARMv7: movw r[[reg5:[0-9]+]],
52 ; ARMv7: movt r[[reg5]],
53 ; ARMv7: add r[[reg5]], pc, r[[reg5]]
54 ; ARMv7: ldr r[[reg5]], [r[[reg5]]]
56 ; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
58 ; ARMv7-ELF: ldr r[[reg6:[0-9]+]], [pc, r[[reg5]]]
59 ; ARMv7-ELF: ldr r0, [r[[reg5]]]
|
| /external/u-boot/board/freescale/ls2080aqds/ |
| D | ls2080aqds.c | 175 u8 reg5; in config_board_mux() local
177 reg5 = QIXIS_READ(brdcfg[5]); in config_board_mux()
181 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); in config_board_mux()
184 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); in config_board_mux()
191 QIXIS_WRITE(brdcfg[5], reg5); in config_board_mux()
|
| /external/u-boot/board/freescale/ls2080ardb/ |
| D | ls2080ardb.c | 183 u8 reg5; in config_board_mux() local
185 reg5 = QIXIS_READ(brdcfg[5]); in config_board_mux()
189 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC); in config_board_mux()
192 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI); in config_board_mux()
199 QIXIS_WRITE(brdcfg[5], reg5); in config_board_mux()
|
| /external/libyuv/files/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeWx16_MSA()
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
137 res8 = (v16u8)__msa_ilvr_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
138 res9 = (v16u8)__msa_ilvl_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeUVWx16_MSA()
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
[all …]
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| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
795 reg5 = (v8u16)__msa_ilvod_b(zero, (v16i8)vec1); in ARGBToYRow_MSA()
801 reg5 *= const_0x42; in ARGBToYRow_MSA()
805 reg1 += reg5; in ARGBToYRow_MSA()
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
863 reg5 = __msa_hadd_u_h(vec1, vec1); in ARGBToUVRow_MSA()
891 reg5 += __msa_hadd_u_h(vec1, vec1); in ARGBToUVRow_MSA()
897 reg5 = (v8u16)__msa_srai_h((v8i16)reg5, 2); in ARGBToUVRow_MSA()
905 reg9 += reg5 * const_0x26; in ARGBToUVRow_MSA()
911 reg5 *= const_0x70; in ARGBToUVRow_MSA()
[all …]
|
| D | scale_msa.cc | 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
162 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
166 reg5 += reg7; in ScaleARGBRowDownEvenBox_MSA()
168 reg5 = (v8u16)__msa_srari_h((v8i16)reg5, 2); in ScaleARGBRowDownEvenBox_MSA()
169 dst0 = (v16u8)__msa_pckev_b((v16i8)reg5, (v16i8)reg4); in ScaleARGBRowDownEvenBox_MSA()
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeWx16_MSA()
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
137 res8 = (v16u8)__msa_ilvr_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
138 res9 = (v16u8)__msa_ilvl_w((v4i32)reg5, (v4i32)reg1); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeUVWx16_MSA()
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
[all …]
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| D | scale_msa.cc | 141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
170 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
174 reg5 += reg7; in ScaleARGBRowDownEvenBox_MSA()
176 reg5 = (v8u16)__msa_srari_h((v8i16)reg5, 2); in ScaleARGBRowDownEvenBox_MSA()
177 dst0 = (v16u8)__msa_pckev_b((v16i8)reg5, (v16i8)reg4); in ScaleARGBRowDownEvenBox_MSA()
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
706 reg5 = (v16u8)__msa_ilvl_b((v16i8)src2, (v16i8)src0); in ScaleARGBFilterCols_MSA()
710 tmp1 = __msa_dotp_u_h(reg5, mult1); in ScaleARGBFilterCols_MSA()
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
807 reg5 = (v8i16)__msa_dotp_u_h(vec5, const2); in ScaleRowDown34_0_Box_MSA()
[all …]
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| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
795 reg5 = (v8u16)__msa_ilvod_b(zero, (v16i8)vec1); in ARGBToYRow_MSA()
801 reg5 *= const_0x42; in ARGBToYRow_MSA()
805 reg1 += reg5; in ARGBToYRow_MSA()
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
863 reg5 = __msa_hadd_u_h(vec1, vec1); in ARGBToUVRow_MSA()
891 reg5 += __msa_hadd_u_h(vec1, vec1); in ARGBToUVRow_MSA()
897 reg5 = (v8u16)__msa_srai_h((v8i16)reg5, 2); in ARGBToUVRow_MSA()
905 reg9 += reg5 * const_0x26; in ARGBToUVRow_MSA()
911 reg5 *= const_0x70; in ARGBToUVRow_MSA()
[all …]
|
| /external/v8/src/interpreter/ |
| D | bytecode-register.cc | 98 Register reg4, Register reg5) { in AreContiguous() argument
108 if (reg5.is_valid() && reg4.index() + 1 != reg5.index()) { in AreContiguous()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/ |
| D | dwarfdump-debug-frame-simple.test | 21 ; FRAMES-NEXT: DW_CFA_offset: reg5 -8
23 ; FRAMES-NEXT: DW_CFA_def_cfa_register: reg5
|
| /external/llvm/test/DebugInfo/ |
| D | dwarfdump-debug-frame-simple.test | 22 ; FRAMES-NEXT: DW_CFA_offset: reg5 -8
24 ; FRAMES-NEXT: DW_CFA_def_cfa_register: reg5
|
| /external/u-boot/board/freescale/p2041rdb/ |
| D | cpld.c | 51 u8 reg5 = CPLD_READ(sw_ctl_on); in __cpld_set_altbank() local
53 CPLD_WRITE(sw_ctl_on, reg5 | CPLD_SWITCH_BANK_ENABLE); in __cpld_set_altbank()
|
| /external/u-boot/arch/arm/lib/ |
| D | memcpy.S | 24 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
25 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
36 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
37 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | pv.ll | 6 …eg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg %reg5, <4 x float> inreg …
24 %16 = extractelement <4 x float> %reg5, i32 0
25 %17 = extractelement <4 x float> %reg5, i32 1
26 %18 = extractelement <4 x float> %reg5, i32 2
27 %19 = extractelement <4 x float> %reg5, i32 3
|