| /external/u-boot/drivers/gpio/ |
| D | sh_pfc.c | 33 unsigned long reg_width) in gpio_read_raw_reg() argument
35 switch (reg_width) { in gpio_read_raw_reg()
50 unsigned long reg_width, in gpio_write_raw_reg() argument
53 switch (reg_width) { in gpio_write_raw_reg()
74 pos = dr->reg_width - (in_pos + 1); in gpio_read_bit()
77 dr->reg + offset, pos, dr->reg_width); in gpio_read_bit()
80 dr->reg_width) >> pos) & 1; in gpio_read_bit()
88 pos = dr->reg_width - (in_pos + 1); in gpio_write_bit()
92 dr->reg, !!value, pos, dr->reg_width); in gpio_write_bit()
99 gpio_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow); in gpio_write_bit()
[all …]
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| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| D | radeon_blit.c | 252 float reg_width, float reg_height, in calc_tex_coords() argument
256 buf[1] = buf[0] + reg_width / img_width; in calc_tex_coords()
270 unsigned reg_width, unsigned reg_height, in emit_draw_packet() argument
279 reg_width, reg_height, in emit_draw_packet()
287 verts[4] = dst_x_offset + reg_width; in emit_draw_packet()
292 verts[8] = dst_x_offset + reg_width; in emit_draw_packet()
350 unsigned reg_width, in r100_blit() argument
367 if (reg_width + src_x_offset > src_width) in r100_blit()
368 reg_width = src_width - src_x_offset; in r100_blit()
371 if (reg_width + dst_x_offset > dst_width) in r100_blit()
[all …]
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| D | radeon_common_context.h | 476 unsigned reg_width,
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| /external/u-boot/drivers/reset/ |
| D | reset-socfpga.c | 34 int reg_width = sizeof(u32); in socfpga_reset_assert() local
35 int bank = id / (reg_width * BITS_PER_BYTE); in socfpga_reset_assert()
36 int offset = id % (reg_width * BITS_PER_BYTE); in socfpga_reset_assert()
46 int reg_width = sizeof(u32); in socfpga_reset_deassert() local
47 int bank = id / (reg_width * BITS_PER_BYTE); in socfpga_reset_deassert()
48 int offset = id % (reg_width * BITS_PER_BYTE); in socfpga_reset_deassert()
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| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| D | r200_blit.c | 404 float reg_width, float reg_height, in calc_tex_coords() argument
408 buf[1] = buf[0] + reg_width / img_width; in calc_tex_coords()
422 unsigned reg_width, unsigned reg_height, in emit_draw_packet() argument
431 reg_width, reg_height, in emit_draw_packet()
439 verts[4] = dst_x_offset + reg_width; in emit_draw_packet()
444 verts[8] = dst_x_offset + reg_width; in emit_draw_packet()
499 unsigned reg_width, in r200_blit() argument
516 if (reg_width + src_x_offset > src_width) in r200_blit()
517 reg_width = src_width - src_x_offset; in r200_blit()
520 if (reg_width + dst_x_offset > dst_width) in r200_blit()
[all …]
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| D | radeon_common_context.h | 476 unsigned reg_width,
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| /external/libcxx/test/std/experimental/simd/simd.abi/ |
| D | vector_extension.pass.cpp | 21 constexpr inline int reg_width() { in reg_width() function
53 ex::__simd_abi<ex::_StorageKind::_VecExt, reg_width()>>::value,
58 ex::__simd_abi<ex::_StorageKind::_Array, reg_width()>>::value,
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| /external/u-boot/include/ |
| D | sh_pfc.h | 45 unsigned long reg, reg_width, field_width; member
52 .reg = r, .reg_width = r_width, .field_width = f_width, \
57 .reg = r, .reg_width = r_width, \
63 unsigned long reg, reg_width, reg_shadow; member
69 .reg = r, .reg_width = r_width, \
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| /external/u-boot/drivers/pinctrl/renesas/ |
| D | pfc.c | 89 u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width) in sh_pfc_read_raw_reg() argument
91 switch (reg_width) { in sh_pfc_read_raw_reg()
104 void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width, in sh_pfc_write_raw_reg() argument
107 switch (reg_width) { in sh_pfc_write_raw_reg()
150 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); in sh_pfc_config_reg_helper()
153 *posp = crp->reg_width; in sh_pfc_config_reg_helper()
173 crp->reg, value, field, crp->reg_width, crp->field_width); in sh_pfc_write_config_reg()
178 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width); in sh_pfc_write_config_reg()
185 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); in sh_pfc_write_config_reg()
197 unsigned int r_width = config_reg->reg_width; in sh_pfc_get_config_reg()
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| D | sh_pfc.h | 98 u8 reg_width, field_width; member
114 .reg = r, .reg_width = r_width, .field_width = f_width, \
129 .reg = r, .reg_width = r_width, \
166 u8 reg_width; member
179 .reg = r, .reg_width = r_width, \
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_fs_reg_allocate.cpp | 49 int reg_width = dispatch_width / 8; in assign_regs_trivial() local
52 hw_reg_mapping[0] = ALIGN(this->first_non_payload_grf, reg_width); in assign_regs_trivial()
471 int reg_width = v->dispatch_width / 8; in get_used_mrfs() local
479 if (reg_width == 2) { in get_used_mrfs()
539 int reg_width = dispatch_width / 8; in assign_regs() local
541 int payload_node_count = ALIGN(this->first_non_payload_grf, reg_width); in assign_regs()
542 int rsi = _mesa_logbase2(reg_width); /* Which compiler->fs_reg_sets[] to use */ in assign_regs()
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| D | brw_fs_visitor.cpp | 94 int reg_width = dispatch_width / 8; in emit_dummy_fs() local
99 bld.MOV(fs_reg(MRF, 2 + i * reg_width, BRW_REGISTER_TYPE_F), in emit_dummy_fs()
108 write->mlen = 4 * reg_width; in emit_dummy_fs()
112 write->mlen = 2 + 4 * reg_width; in emit_dummy_fs()
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| D | brw_fs.cpp | 1001 int reg_width = dispatch_width / 8; in vgrf() local
1002 return fs_reg(VGRF, alloc.allocate(type_size_scalar(type) * reg_width), in vgrf()
4190 unsigned reg_width = bld.dispatch_width() / 8; in lower_sampler_logical_send_gen7() local
4216 if (!inst->eot && regs_written(inst) != 4 * reg_width) { in lower_sampler_logical_send_gen7()
4217 assert(regs_written(inst) % reg_width == 0); in lower_sampler_logical_send_gen7()
4218 unsigned mask = ~((1 << (regs_written(inst) / reg_width)) - 1) & 0xf; in lower_sampler_logical_send_gen7()
4392 if (reg_width == 2) in lower_sampler_logical_send_gen7()
4393 mlen = length * reg_width - header_size; in lower_sampler_logical_send_gen7()
4395 mlen = length * reg_width; in lower_sampler_logical_send_gen7()
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| D | brw_fs_generator.cpp | 77 const unsigned reg_width = REG_SIZE / (reg->stride * type_sz(reg->type)); in brw_reg_from_fs_reg() local
93 const unsigned width = MIN2(reg_width, phys_width); in brw_reg_from_fs_reg()
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| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 1840 int64_t ExtendValue(unsigned reg_width,
|