| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetRegisterInfo.cpp | 61 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ in getMinimalPhysRegClass()
87 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), in getAllocatableSet()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCRegisterInfo.h | 290 regclass_iterator regclass_begin() const { return Classes; } in regclass_begin() function
294 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 427 regclass_iterator regclass_begin() const { return Classes; } in regclass_begin() function
430 return make_range(regclass_begin(), regclass_end()); in regclasses()
434 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | RenderMachineFunction.cpp | 248 for (TargetRegisterInfo::regclass_iterator rcItr = tri->regclass_begin(), in translateRegClassNamesToCurrentFunction()
351 for (TargetRegisterInfo::regclass_iterator rcItr = tri->regclass_begin(), in initWorst()
370 for (TargetRegisterInfo::regclass_iterator rc1Itr = tri->regclass_begin(), in initWorst()
376 for (TargetRegisterInfo::regclass_iterator rc2Itr = tri->regclass_begin(); in initWorst()
433 for (TargetRegisterInfo::regclass_iterator rcItr = tri->regclass_begin(), in initCapacity()
479 rcItr = tri->regclass_begin(), in resetPressureAndLiveStates()
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| D | VirtRegMap.cpp | 82 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in runOnMachineFunction()
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| D | MachineLICM.cpp | 330 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in runOnMachineFunction()
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| D | RegAllocLinearScan.cpp | 407 for (TargetRegisterInfo::regclass_iterator RCI = tri_->regclass_begin(), in INITIALIZE_PASS_DEPENDENCY()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 677 regclass_iterator regclass_begin() const { return RegClassBegin; } in regclass_begin() function
680 return make_range(regclass_begin(), regclass_end()); in regclasses()
684 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 448 regclass_iterator regclass_begin() const { return RegClassBegin; } in regclass_begin() function
452 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetRegisterInfo.cpp | 134 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ in getMinimalPhysRegClass()
164 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), in getAllocatableSet()
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| D | RegisterClassInfo.cpp | 160 RI = TRI->regclass_begin(), RE = TRI->regclass_end(); RI != RE; ++RI) { in computePSetLimit()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | ResourcePriorityQueue.cpp | 60 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in ResourcePriorityQueue()
367 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in regPressureDelta()
374 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in regPressureDelta()
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| D | ScheduleDAGRRList.cpp | 1662 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in RegReductionPQBase()
1930 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in dumpRegPressure()
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| D | TargetLowering.cpp | 2357 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), in getRegForInlineAsmConstraint()
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| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 408 regclass_iterator regclass_begin() const { return Classes; } in regclass_begin() function
412 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 640 regclass_iterator regclass_begin() const { return RegClassBegin; } in regclass_begin() function
644 return (unsigned)(regclass_end()-regclass_begin()); in getNumRegClasses()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonBlockRanges.cpp | 233 for (auto I = TRI.regclass_begin(), E = TRI.regclass_end(); I != E; ++I) { in HexagonBlockRanges()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | ScheduleDAGRRList.cpp | 1550 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in RegReductionPQBase()
1820 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in dumpRegPressure()
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| D | TargetLowering.cpp | 2757 for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), in getRegForInlineAsmConstraint()
|