| /external/u-boot/board/xilinx/zynqmp/zynqmp-zcu100-revC/ |
| D | psu_init_gpl.c | 686 unsigned int regval = 0; in psu_ddr_phybringup_data() local
723 regval = Xil_In32(0xFD070018); in psu_ddr_phybringup_data()
724 while ((regval & 0x1) != 0x0) in psu_ddr_phybringup_data()
725 regval = Xil_In32(0xFD070018); in psu_ddr_phybringup_data()
727 regval = Xil_In32(0xFD070018); in psu_ddr_phybringup_data()
728 regval = Xil_In32(0xFD070018); in psu_ddr_phybringup_data()
729 regval = Xil_In32(0xFD070018); in psu_ddr_phybringup_data()
730 regval = Xil_In32(0xFD070018); in psu_ddr_phybringup_data()
731 regval = Xil_In32(0xFD070018); in psu_ddr_phybringup_data()
732 regval = Xil_In32(0xFD070018); in psu_ddr_phybringup_data()
[all …]
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| /external/u-boot/arch/arm/mach-omap2/omap3/ |
| D | emif4.c | 65 unsigned int regval; in do_emif4_init() local
67 regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS | in do_emif4_init()
69 writel(regval, &emif4_base->ddr_phyctrl1); in do_emif4_init()
70 writel(regval, &emif4_base->ddr_phyctrl1_shdw); in do_emif4_init()
74 regval = readl(&emif4_base->sdram_iodft_tlgc); in do_emif4_init()
75 regval |= (1<<10); in do_emif4_init()
76 writel(regval, &emif4_base->sdram_iodft_tlgc); in do_emif4_init()
82 regval |= (1<<0); in do_emif4_init()
83 writel(regval, &emif4_base->sdram_iodft_tlgc); in do_emif4_init()
85 regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD | in do_emif4_init()
[all …]
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| /external/u-boot/drivers/adc/ |
| D | meson-saradc.c | 183 u32 regval; in meson_saradc_get_fifo_count() local
185 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_saradc_get_fifo_count()
187 return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval); in meson_saradc_get_fifo_count()
246 uint regval, timeout = 10000; in meson_saradc_wait_busy_clear() local
255 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_saradc_wait_busy_clear()
256 } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--); in meson_saradc_wait_busy_clear()
267 uint regval, fifo_chan, fifo_val, count; in meson_saradc_read_raw_sample() local
280 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); in meson_saradc_read_raw_sample()
281 fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval); in meson_saradc_read_raw_sample()
288 fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval); in meson_saradc_read_raw_sample()
[all …]
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| /external/u-boot/arch/arm/mach-at91/armv7/ |
| D | clock.c | 197 u32 regval, status; in at91_enable_periph_generated_clk() local
212 regval = readl(&pmc->pcr); in at91_enable_periph_generated_clk()
213 regval &= ~AT91_PMC_PCR_GCKCSS; in at91_enable_periph_generated_clk()
214 regval &= ~AT91_PMC_PCR_GCKDIV; in at91_enable_periph_generated_clk()
218 regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK; in at91_enable_periph_generated_clk()
221 regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK; in at91_enable_periph_generated_clk()
224 regval |= AT91_PMC_PCR_GCKCSS_PLLA_CLK; in at91_enable_periph_generated_clk()
227 regval |= AT91_PMC_PCR_GCKCSS_UPLL_CLK; in at91_enable_periph_generated_clk()
230 regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK; in at91_enable_periph_generated_clk()
233 regval |= AT91_PMC_PCR_GCKCSS_AUDIO_CLK; in at91_enable_periph_generated_clk()
[all …]
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| /external/u-boot/board/keymile/km_arm/ |
| D | fpga_config.c | 36 u8 regval; in boco_clear_bits() local
39 ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); in boco_clear_bits()
45 regval &= ~flags; in boco_clear_bits()
46 ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); in boco_clear_bits()
59 u8 regval; in boco_set_bits() local
62 ret = i2c_read(BOCO_ADDR, reg, 1, ®val, 1); in boco_set_bits()
68 regval |= flags; in boco_set_bits()
69 ret = i2c_write(BOCO_ADDR, reg, 1, ®val, 1); in boco_set_bits()
88 u8 regval; in fpga_done() local
94 ret = i2c_read(BOCO_ADDR, SPI_REG, 1, ®val, 1); in fpga_done()
[all …]
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| /external/u-boot/cmd/ |
| D | mii.c | 122 ushort regval,
129 ushort regval);
146 ushort regval, in dump_reg() argument
155 prd->regno, regval, prd->name); in dump_reg()
164 regval & mask_in_place, in dump_reg()
167 if (special_field(prd->regno, pdesc, regval)) { in dump_reg()
175 (regval & mask_in_place) >> pdesc->lo, in dump_reg()
196 ushort regval) in special_field() argument
199 ushort speed_bits = regval & (BMCR_SPEED1000 | BMCR_SPEED100); in special_field()
202 (regval >> 6) & 1, in special_field()
[all …]
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| /external/u-boot/arch/mips/mach-ath79/ar934x/ |
| D | clk.c | 228 static u32 ar934x_cpupll_to_hz(const u32 regval) in ar934x_cpupll_to_hz() argument
230 const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in ar934x_cpupll_to_hz()
232 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_cpupll_to_hz()
234 const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & in ar934x_cpupll_to_hz()
236 const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in ar934x_cpupll_to_hz()
243 static u32 ar934x_ddrpll_to_hz(const u32 regval) in ar934x_ddrpll_to_hz() argument
245 const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & in ar934x_ddrpll_to_hz()
247 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_ddrpll_to_hz()
249 const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & in ar934x_ddrpll_to_hz()
251 const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & in ar934x_ddrpll_to_hz()
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| /external/u-boot/arch/arm/mach-at91/ |
| D | clock.c | 19 u32 regval; in at91_periph_clk_enable() local
29 regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value; in at91_periph_clk_enable()
31 writel(regval, &pmc->pcr); in at91_periph_clk_enable()
42 u32 regval; in at91_periph_clk_disable() local
47 regval = AT91_PMC_PCR_CMD_WRITE | id; in at91_periph_clk_disable()
49 writel(regval, &pmc->pcr); in at91_periph_clk_disable()
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| /external/u-boot/arch/arm/cpu/armv8/zynqmp/ |
| D | psu_spl_init.c | 53 unsigned long regval = 0; in psu_mask_write() local
55 regval = readl(offset); in psu_mask_write()
56 regval &= ~(mask); in psu_mask_write()
57 regval |= (val & mask); in psu_mask_write()
58 writel(regval, offset); in psu_mask_write()
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| /external/u-boot/drivers/sound/ |
| D | max98095.c | 146 u8 regval; in max98095_hw_params() local
177 if (rate_value(rate, ®val)) { in max98095_hw_params()
185 M98095_CLKMODE_MASK, regval); in max98095_hw_params()
257 u8 regval = 0; in max98095_set_fmt() local
291 regval |= M98095_DAI_MAS; in max98095_set_fmt()
302 regval |= M98095_DAI_DLY; in max98095_set_fmt()
315 regval |= M98095_DAI_WCI; in max98095_set_fmt()
318 regval |= M98095_DAI_BCI; in max98095_set_fmt()
321 regval |= M98095_DAI_BCI | M98095_DAI_WCI; in max98095_set_fmt()
331 regval); in max98095_set_fmt()
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| /external/u-boot/drivers/net/phy/ |
| D | atheros.c | 57 int regval; in ar8035_config() local
62 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in ar8035_config()
63 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); in ar8035_config()
66 regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); in ar8035_config()
67 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); in ar8035_config()
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| D | micrel_ksz90x1.c | 114 u16 regval = 0; in ksz90x1_of_config_group() local
124 regval |= ofcfg->grp[i].dflt << offset; in ksz90x1_of_config_group()
130 regval |= max << offset; in ksz90x1_of_config_group()
132 regval |= (val[i] / ps_to_regval) << offset; in ksz90x1_of_config_group()
140 return drv->writeext(phydev, 0, ofcfg->devad, ofcfg->reg, regval); in ksz90x1_of_config_group()
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| /external/u-boot/arch/arm/mach-omap2/am33xx/ |
| D | board.c | 344 u32 regval; in uart_soft_reset() local
346 regval = readl(&uart_base->uartsyscfg); in uart_soft_reset()
347 regval |= UART_RESET; in uart_soft_reset()
348 writel(regval, &uart_base->uartsyscfg); in uart_soft_reset()
354 regval = readl(&uart_base->uartsyscfg); in uart_soft_reset()
355 regval |= UART_SMART_IDLE_EN; in uart_soft_reset()
356 writel(regval, &uart_base->uartsyscfg); in uart_soft_reset()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zcu106-revA/ |
| D | psu_init_gpl.c | 646 unsigned int regval = 0; in psu_ddr_phybringup_data() local
661 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
662 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
663 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
675 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
676 while ((regval & 0x80004001) != 0x80004001) in psu_ddr_phybringup_data()
677 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
690 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
691 while ((regval & 0x80000C01) != 0x80000C01) in psu_ddr_phybringup_data()
692 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-revA/ |
| D | psu_init_gpl.c | 652 unsigned int regval = 0; in psu_ddr_phybringup_data() local
686 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
687 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
688 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
700 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
701 while ((regval & 0x80004001) != 0x80004001) in psu_ddr_phybringup_data()
702 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
714 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
715 while ((regval & 0x80000C01) != 0x80000C01) in psu_ddr_phybringup_data()
716 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
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| /external/u-boot/board/Arcturus/ucp1020/ |
| D | ucp1020.c | 150 int regval; in board_phy_config() local
157 regval = in board_phy_config()
172 printf("0x%x", (regval & 0x1f)); in board_phy_config()
183 regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000); in board_phy_config()
184 if (regval >= 0) in board_phy_config()
185 printf(" (ADDR 0x%x) ", regval & 0x1f); in board_phy_config()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zcu104-revA/ |
| D | psu_init_gpl.c | 647 unsigned int regval = 0; in psu_ddr_phybringup_data() local
680 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
681 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
682 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
694 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
695 while ((regval & 0x80004001) != 0x80004001) in psu_ddr_phybringup_data()
697 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
710 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
711 while ((regval & 0x80000C01) != 0x80000C01) in psu_ddr_phybringup_data()
713 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
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| /external/u-boot/arch/arm/mach-mvebu/armada3700/ |
| D | cpu.c | 77 u32 regval; in get_ref_clk() local
79 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >> in get_ref_clk()
82 if (regval == MVEBU_XTAL_CLOCK_25MHZ) in get_ref_clk()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm018-dc4/ |
| D | psu_init_gpl.c | 649 unsigned int regval = 0; in psu_ddr_phybringup_data() local
682 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
683 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
684 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
696 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
697 while ((regval & 0x80004001) != 0x80004001) in psu_ddr_phybringup_data()
699 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
712 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
713 while ((regval & 0x80000C01) != 0x80000C01) in psu_ddr_phybringup_data()
715 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm015-dc1/ |
| D | psu_init_gpl.c | 661 unsigned int regval = 0; in psu_ddr_phybringup_data() local
694 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
695 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
696 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
708 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
709 while ((regval & 0x80004001) != 0x80004001) in psu_ddr_phybringup_data()
711 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
724 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
725 while ((regval & 0x80000C01) != 0x80000C01) in psu_ddr_phybringup_data()
727 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm019-dc5/ |
| D | psu_init_gpl.c | 675 unsigned int regval = 0; in psu_ddr_phybringup_data() local
708 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
709 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
710 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
722 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
723 while ((regval & 0x80004001) != 0x80004001) in psu_ddr_phybringup_data()
725 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
738 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
739 while ((regval & 0x80000C01) != 0x80000C01) in psu_ddr_phybringup_data()
741 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm017-dc3/ |
| D | psu_init_gpl.c | 649 unsigned int regval = 0; in psu_ddr_phybringup_data() local
682 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
683 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
684 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
696 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
697 while ((regval & 0x80004001) != 0x80004001) in psu_ddr_phybringup_data()
699 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
712 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
713 while ((regval & 0x80000C01) != 0x80000C01) in psu_ddr_phybringup_data()
715 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zc1751-xm016-dc2/ |
| D | psu_init_gpl.c | 649 unsigned int regval = 0; in psu_ddr_phybringup_data() local
682 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
683 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
684 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
696 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
697 while ((regval & 0x80004001) != 0x80004001) in psu_ddr_phybringup_data()
699 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
712 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
713 while ((regval & 0x80000C01) != 0x80000C01) in psu_ddr_phybringup_data()
715 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zcu102-rev1.0/ |
| D | psu_init_gpl.c | 727 unsigned int regval = 0; in psu_ddr_phybringup_data() local
765 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
766 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
767 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
779 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
780 while ((regval & 0x80004001) != 0x80004001) in psu_ddr_phybringup_data()
782 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
795 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
796 while ((regval & 0x80000C01) != 0x80000C01) in psu_ddr_phybringup_data()
798 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
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| /external/u-boot/board/xilinx/zynqmp/zynqmp-zc1254-revA/ |
| D | psu_init_gpl.c | 407 unsigned int regval = 0; in psu_ddr_phybringup_data() local
440 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
441 while (regval != 0x80000FFF) in psu_ddr_phybringup_data()
442 regval = Xil_In32(0xFD080030); in psu_ddr_phybringup_data()
|