Home
last modified time | relevance | path

Searched refs:reset_manager_base (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/arch/arm/mach-socfpga/
Dreset_manager_arria10.c18 static const struct socfpga_reset_manager *reset_manager_base = variable
131 setbits_le32(&reset_manager_base->per1modrst, in socfpga_watchdog_disable()
138 clrbits_le32(&reset_manager_base->brgmodrst, in socfpga_reset_deassert_noc_ddr_scheduler()
147 val = readl(&reset_manager_base->per1modrst); in socfpga_is_wdt_in_reset()
183 setbits_le32(&reset_manager_base->per0modrst, eccmask); in socfpga_emac_manage_reset()
184 setbits_le32(&reset_manager_base->per0modrst, emacmask); in socfpga_emac_manage_reset()
187 clrbits_le32(&reset_manager_base->per0modrst, emacmask); in socfpga_emac_manage_reset()
188 clrbits_le32(&reset_manager_base->per0modrst, eccmask); in socfpga_emac_manage_reset()
221 clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr); in socfpga_reset_deassert_bridges_handoff()
243 setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK); in socfpga_reset_assert_fpga_connected_peripherals()
[all …]
Dreset_manager_s10.c15 static const struct socfpga_reset_manager *reset_manager_base = variable
26 reg = &reset_manager_base->mpumodrst; in socfpga_per_reset()
28 reg = &reset_manager_base->per0modrst; in socfpga_per_reset()
30 reg = &reset_manager_base->per1modrst; in socfpga_per_reset()
32 reg = &reset_manager_base->brgmodrst; in socfpga_per_reset()
53 &reset_manager_base->per0modrst); in socfpga_per_reset_all()
54 writel(~l4wd0, &reset_manager_base->per0modrst); in socfpga_per_reset_all()
55 writel(0xffffffff, &reset_manager_base->per1modrst); in socfpga_per_reset_all()
65 clrbits_le32(&reset_manager_base->brgmodrst, ~0); in socfpga_bridges_reset()
88 setbits_le32(&reset_manager_base->brgmodrst, in socfpga_bridges_reset()
[all …]
Dreset_manager_gen5.c13 static const struct socfpga_reset_manager *reset_manager_base = variable
26 reg = &reset_manager_base->mpu_mod_reset; in socfpga_per_reset()
29 reg = &reset_manager_base->per_mod_reset; in socfpga_per_reset()
32 reg = &reset_manager_base->per2_mod_reset; in socfpga_per_reset()
35 reg = &reset_manager_base->brg_mod_reset; in socfpga_per_reset()
38 reg = &reset_manager_base->misc_mod_reset; in socfpga_per_reset()
60 writel(~l4wd0, &reset_manager_base->per_mod_reset); in socfpga_per_reset_all()
61 writel(0xffffffff, &reset_manager_base->per2_mod_reset); in socfpga_per_reset_all()
69 writel(0, &reset_manager_base->per_mod_reset); in reset_deassert_peripherals_handoff()
84 writel(0xffffffff, &reset_manager_base->brg_mod_reset); in socfpga_bridges_reset()
[all …]
Dreset_manager.c18 static const struct socfpga_reset_manager *reset_manager_base = variable
33 &reset_manager_base->ctrl); in reset_cpu()
Dmisc_gen5.c228 static struct socfpga_reset_manager *reset_manager_base = variable
274 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset); in do_bridge()
281 writel(0, &reset_manager_base->brg_mod_reset); in do_bridge()