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Searched refs:ret0 (Results 1 – 25 of 36) sorted by relevance

12

/external/libffi/src/pa/
Dlinux.S99 ldw -52(%r3), %ret0 /* %ret0 <- rvalue */
113 stw %ret0, 0(%r20)
118 stb %ret0, 0(%r20)
123 sth %ret0, 0(%r20)
137 stw %ret0, 0(%r20)
144 extru %ret0, 23, 8, %r22
147 stb %ret0, 0(%r20)
152 extru %ret0, 15, 8, %r22
154 extru %ret0, 23, 8, %r22
157 stb %ret0, 0(%r20)
[all …]
Dhpux32.S105 ldw -52(%r3), %ret0 ; %ret0 <- rvalue
120 stw %ret0, 0(%r20)
125 stb %ret0, 0(%r20)
130 sth %ret0, 0(%r20)
144 stw %ret0, 0(%r20)
151 extru %ret0, 23, 8, %r22
154 stb %ret0, 0(%r20)
159 extru %ret0, 15, 8, %r22
161 extru %ret0, 23, 8, %r22
164 stb %ret0, 0(%r20)
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/pa/
Dlinux.S99 ldw -52(%r3), %ret0 /* %ret0 <- rvalue */
113 stw %ret0, 0(%r20)
118 stb %ret0, 0(%r20)
123 sth %ret0, 0(%r20)
137 stw %ret0, 0(%r20)
144 extru %ret0, 23, 8, %r22
147 stb %ret0, 0(%r20)
152 extru %ret0, 15, 8, %r22
154 extru %ret0, 23, 8, %r22
157 stb %ret0, 0(%r20)
[all …]
Dhpux32.S105 ldw -52(%r3), %ret0 ; %ret0 <- rvalue
120 stw %ret0, 0(%r20)
125 stb %ret0, 0(%r20)
130 sth %ret0, 0(%r20)
144 stw %ret0, 0(%r20)
151 extru %ret0, 23, 8, %r22
154 stb %ret0, 0(%r20)
159 extru %ret0, 15, 8, %r22
161 extru %ret0, 23, 8, %r22
164 stb %ret0, 0(%r20)
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/PTX/
Dintrinsic.ll4 ; CHECK: mov.u32 %ret0, %tid.x;
11 ; CHECK: mov.u32 %ret0, %tid.y;
18 ; CHECK: mov.u32 %ret0, %tid.z;
25 ; CHECK: mov.u32 %ret0, %tid.w;
32 ; CHECK: mov.u32 %ret0, %ntid.x;
39 ; CHECK: mov.u32 %ret0, %ntid.y;
46 ; CHECK: mov.u32 %ret0, %ntid.z;
53 ; CHECK: mov.u32 %ret0, %ntid.w;
60 ; CHECK: mov.u32 %ret0, %laneid;
67 ; CHECK: mov.u32 %ret0, %warpid;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dsad.ll12 %ret0 = sub i32 %t0, %t1
13 %ret = add i32 %ret0, %c
28 %ret0 = sub i32 %t0, %t1
29 %ret = add i32 %ret0, 20
41 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
43 %ret = add i32 %ret0, %c
61 %ret0 = sub i32 %t0, %t1
62 store volatile i32 %ret0, i32 addrspace(5)*undef
63 %ret = add i32 %ret0, %c
78 %ret0 = sub i32 %t0, %t1
[all …]
Dmulti-divergent-exit-region.ll568 br i1 %divergent.cond0, label %divergent.ret0, label %divergent.ret1
570 divergent.ret0:
603 br i1 %divergent.cond2, label %divergent.ret0, label %divergent.endif
607 br label %divergent.ret0
609 divergent.ret0:
629 ; IR: br i1 %11, label %uniform.endif, label %uniform.ret0
653 br i1 %uniform.cond2, label %uniform.ret0, label %uniform.endif
657 br label %uniform.ret0
659 uniform.ret0:
Drewrite-out-arguments.ll148 ; CHECK: br i1 %arg0, label %ret0, label %ret1
150 ; CHECK: ret0:
162 br i1 %arg0, label %ret0, label %ret1
164 ret0:
261 ; CHECK: ret0:
268 br i1 %arg0, label %ret0, label %ret1
270 ret0:
767 ; CHECK: ret0:
780 br i1 %cond, label %ret0, label %ret1
782 ret0:
/external/u-boot/board/compulab/cl-som-am57x/
Dcl-som-am57x.c42 int ret0, ret1; in board_mmc_init() local
44 ret0 = omap_mmc_init(0, 0, 0, SB_SOM_CD_GPIO, SB_SOM_WP_GPIO); in board_mmc_init()
45 if (ret0) in board_mmc_init()
52 return ret0 && ret1; in board_mmc_init()
/external/u-boot/board/compulab/cm_t54/
Dcm_t54.c105 int ret0, ret1; in board_mmc_init() local
107 ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO); in board_mmc_init()
108 if (ret0) in board_mmc_init()
115 if (ret0 && ret1) in board_mmc_init()
/external/llvm/test/Transforms/InstCombine/
D2011-09-03-Trampoline.ll49 ; CHECK: %ret0 = call i32 @f(i8* nest null, i32 %n)
52 %ret0 = call i32 %function0(i32 %n)
71 %ret0 = call i32 %function0(i32 %n)
84 ; CHECK: %ret0 = call i32 @f(i8* nest null, i32 %n)
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
D2011-09-03-Trampoline.ll49 ; CHECK: %ret0 = call i32 @f(i8* nest null, i32 %n)
52 %ret0 = call i32 %function0(i32 %n)
71 %ret0 = call i32 %function0(i32 %n)
84 ; CHECK: %ret0 = call i32 @f(i8* nest null, i32 %n)
/external/deqp/external/openglcts/data/gl33/
Darrays.test354 float ret0 = a0[2][0];
358 out0 = vec3(ret0, ret1, ret2);
395 float ret0 = a0[2][0];
399 out0 = ivec3(ret0, ret1, ret2);
435 float ret0 = a0[2][0];
439 out0 = bvec3(ret0, ret1, ret2);
714 float ret0 = b0[0][0];
718 out0 = vec3(ret0, ret1, ret2);
767 float ret0 = b0[0][0];
771 out0 = ivec3(ret0, ret1, ret2);
[all …]
/external/deqp/external/openglcts/data/gles3/
Darrays.test354 float ret0 = a0[2][0];
358 out0 = vec3(ret0, ret1, ret2);
395 float ret0 = a0[2][0];
399 out0 = ivec3(ret0, ret1, ret2);
435 float ret0 = a0[2][0];
439 out0 = bvec3(ret0, ret1, ret2);
714 float ret0 = b0[0][0];
718 out0 = vec3(ret0, ret1, ret2);
767 float ret0 = b0[0][0];
771 out0 = ivec3(ret0, ret1, ret2);
[all …]
/external/deqp/external/vulkancts/data/vulkan/glsl/es310/
Darrays.test357 float ret0 = a0[2][0];
361 out0 = vec3(ret0, ret1, ret2);
398 float ret0 = a0[2][0];
402 out0 = ivec3(ret0, ret1, ret2);
439 float ret0 = a0[2][0];
443 out0 = bvec3(ret0, ret1, ret2);
719 float ret0 = b0[0][0];
723 out0 = vec3(ret0, ret1, ret2);
772 float ret0 = b0[0][0];
776 out0 = ivec3(ret0, ret1, ret2);
[all …]
/external/deqp/data/gles3/shaders/
Darrays.test354 float ret0 = a0[2][0];
358 out0 = vec3(ret0, ret1, ret2);
395 float ret0 = a0[2][0];
399 out0 = ivec3(ret0, ret1, ret2);
435 float ret0 = a0[2][0];
439 out0 = bvec3(ret0, ret1, ret2);
714 float ret0 = b0[0][0];
718 out0 = vec3(ret0, ret1, ret2);
767 float ret0 = b0[0][0];
771 out0 = ivec3(ret0, ret1, ret2);
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
D2011-09-03-Trampoline.ll49 ; CHECK: %ret0 = call i32 @f(i8* nest null, i32 %n)
52 %ret0 = call i32 %function0(i32 %n)
71 %ret0 = call i32 %function0(i32 %n)
84 ; CHECK: %ret0 = call i32 @f(i8* nest null, i32 %n)
/external/deqp/data/gles31/shaders/es32/
Darrays_of_arrays.test444 float ret0 = a0[2][0];
448 out0 = vec3(ret0, ret1, ret2);
499 float ret0 = x0[2][0];
503 out0 = ivec3(ret0, ret1, ret2);
547 float ret0 = x0[2][0];
551 out0 = bvec3(ret0, ret1, ret2);
1006 float ret0 = a0[2][0];
1010 out0 = vec3(ret0, ret1, ret2);
1061 float ret0 = x0[2][0];
1065 out0 = ivec3(ret0, ret1, ret2);
[all …]
/external/deqp/data/gles31/shaders/es31/
Darrays_of_arrays.test425 float ret0 = a0[2][0];
429 out0 = vec3(ret0, ret1, ret2);
480 float ret0 = x0[2][0];
484 out0 = ivec3(ret0, ret1, ret2);
528 float ret0 = x0[2][0];
532 out0 = bvec3(ret0, ret1, ret2);
987 float ret0 = a0[2][0];
991 out0 = vec3(ret0, ret1, ret2);
1042 float ret0 = x0[2][0];
1046 out0 = ivec3(ret0, ret1, ret2);
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dmatch.ll78 %ret0 = insertvalue {i32, i1} undef, i32 %vsum3, 0
79 %ret1 = insertvalue {i32, i1} %ret0, i1 %psum3, 1
114 %ret0 = insertvalue {i64, i1} undef, i64 %vsum3, 0
115 %ret1 = insertvalue {i64, i1} %ret0, i1 %psum3, 1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dvar-permute-256.ll76 %ret0 = insertelement <4 x i64> undef, i64 %v0, i32 0
77 %ret1 = insertelement <4 x i64> %ret0, i64 %v1, i32 1
126 %ret0 = insertelement <8 x i32> undef, i32 %v0, i32 0
127 %ret1 = insertelement <8 x i32> %ret0, i32 %v1, i32 1
253 %ret0 = insertelement <16 x i16> undef, i16 %v0, i32 0
254 %ret1 = insertelement <16 x i16> %ret0, i16 %v1, i32 1
409 %ret0 = insertelement <32 x i8> undef, i8 %v0, i32 0
410 %ret1 = insertelement <32 x i8> %ret0, i8 %v1, i32 1
506 %ret0 = insertelement <4 x double> undef, double %v0, i32 0
507 %ret1 = insertelement <4 x double> %ret0, double %v1, i32 1
[all …]
Dknown-bits.ll214 %ret0 = insertvalue {i32, i1} undef, i32 %3, 0
215 %ret1 = insertvalue {i32, i1} %ret0, i1 %4, 1
265 %ret0 = insertvalue {i32, i1} undef, i32 %3, 0
266 %ret1 = insertvalue {i32, i1} %ret0, i1 %4, 1
Dvar-permute-128.ll61 %ret0 = insertelement <2 x i64> undef, i64 %v0, i32 0
62 %ret1 = insertelement <2 x i64> %ret0, i64 %v1, i32 1
122 %ret0 = insertelement <4 x i32> undef, i32 %v0, i32 0
123 %ret1 = insertelement <4 x i32> %ret0, i32 %v1, i32 1
215 %ret0 = insertelement <8 x i16> undef, i16 %v0, i32 0
216 %ret1 = insertelement <8 x i16> %ret0, i16 %v1, i32 1
358 %ret0 = insertelement <16 x i8> undef, i8 %v0, i32 0
359 %ret1 = insertelement <16 x i8> %ret0, i8 %v1, i32 1
422 %ret0 = insertelement <2 x double> undef, double %v0, i32 0
423 %ret1 = insertelement <2 x double> %ret0, double %v1, i32 1
[all …]
/external/swiftshader/third_party/LLVM/test/Transforms/FunctionAttrs/
D2008-12-31-NoCapture.ll45 to label %ret0 unwind label %ret1
46 ret0:
/external/u-boot/drivers/i2c/
Di2c-uclass.c512 int ret, ret0; in i2c_deblock_gpio() local
533 ret0 = i2c_deblock_gpio_loop(&gpios[PIN_SDA], &gpios[PIN_SCL]); in i2c_deblock_gpio()
541 ret = !ret ? ret0 : ret; in i2c_deblock_gpio()

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