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Searched refs:s_sext_i32_i16 (Results 1 – 25 of 31) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dtrunc-combine.ll60 ; GCN: s_sext_i32_i16
61 ; GCN: s_sext_i32_i16
Dsext-in-reg.ll45 ; GCN: s_sext_i32_i16 [[EXTRACT:s[0-9]+]], [[VAL]]
376 ; GCN: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}}
377 ; GCN: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}}
529 ; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
548 ; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
609 ; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
626 ; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
643 ; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
Dmin.ll112 ; SI: s_sext_i32_i16
114 ; SI: s_sext_i32_i16
118 ; VI: s_sext_i32_i16
119 ; VI: s_sext_i32_i16
513 ; GCN-DAG: s_sext_i32_i16 [[EXT_A:s[0-9]+]], [[A]]
514 ; GCN-DAG: s_sext_i32_i16 [[EXT_B:s[0-9]+]], [[B]]
Didiv-licm.ll198 ; GCN-DAG: s_sext_i32_i16
225 ; GCN-DAG: s_sext_i32_i16
Dload-constant-i16.ll165 ; GCN-DAG: s_sext_i32_i16
254 ; GCN-DAG: s_sext_i32_i16
313 ; GCN-DAG: s_sext_i32_i16
362 ; GCN-DAG: s_sext_i32_i16
394 ; GCN-DAG: s_sext_i32_i16
Dashr.v2i16.ll17 ; CIVI-DAG: s_sext_i32_i16
18 ; CIVI-DAG: s_sext_i32_i16
Dsign_extend.ll190 ; GCN-DAG: s_sext_i32_i16
191 ; GCN-DAG: s_sext_i32_i16
Dmax.ll260 ; SI: s_sext_i32_i16
261 ; SI: s_sext_i32_i16
Dsmed3.ll369 ; GCN: s_sext_i32_i16
370 ; GCN: s_sext_i32_i16
371 ; GCN: s_sext_i32_i16
Dwiden-smrd-loads.ll32 ; GCN: s_sext_i32_i16 [[EXT:s[0-9]+]], [[VAL]]
Dmul_uint24-amdgcn.ll25 ; VI: s_sext_i32_i16 s{{[0-9]+}}, [[MUL]]
Dkernel-args.ll132 ; HSA-VI: s_sext_i32_i16 s{{[0-9]+}}, [[VAL]]
/external/llvm/test/MC/AMDGPU/
Dsop1.s143 s_sext_i32_i16 s1, s2 label
/external/llvm/test/CodeGen/AMDGPU/
Dload-constant-i16.ll141 ; GCN-DAG: s_sext_i32_i16
195 ; GCN-DAG: s_sext_i32_i16
230 ; GCN-DAG: s_sext_i32_i16
252 ; GCN-DAG: s_sext_i32_i16
275 ; GCN-DAG: s_sext_i32_i16
Dsign_extend.ll127 ; GCN-DAG: s_sext_i32_i16
128 ; GCN-DAG: s_sext_i32_i16
Dsmed3.ll366 ; GCN: s_sext_i32_i16
367 ; GCN: s_sext_i32_i16
368 ; GCN: s_sext_i32_i16
Dmax.ll260 ; SI: s_sext_i32_i16
261 ; SI: s_sext_i32_i16
Dsext-in-reg.ll44 ; SI: s_sext_i32_i16 [[EXTRACT:s[0-9]+]], [[VAL]]
353 ; SI: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}}
354 ; SI: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dsop1.s146 s_sext_i32_i16 s1, s2 label
Dgfx7_asm_all.s12465 s_sext_i32_i16 s5, s1 label
12468 s_sext_i32_i16 s103, s1 label
12471 s_sext_i32_i16 flat_scratch_lo, s1 label
12474 s_sext_i32_i16 flat_scratch_hi, s1 label
12477 s_sext_i32_i16 vcc_lo, s1 label
12480 s_sext_i32_i16 vcc_hi, s1 label
12483 s_sext_i32_i16 tba_lo, s1 label
12486 s_sext_i32_i16 tba_hi, s1 label
12489 s_sext_i32_i16 tma_lo, s1 label
12492 s_sext_i32_i16 tma_hi, s1 label
[all …]
Dgfx8_asm_all.s13086 s_sext_i32_i16 s5, s1 label
13089 s_sext_i32_i16 s101, s1 label
13092 s_sext_i32_i16 flat_scratch_lo, s1 label
13095 s_sext_i32_i16 flat_scratch_hi, s1 label
13098 s_sext_i32_i16 vcc_lo, s1 label
13101 s_sext_i32_i16 vcc_hi, s1 label
13104 s_sext_i32_i16 tba_lo, s1 label
13107 s_sext_i32_i16 tba_hi, s1 label
13110 s_sext_i32_i16 tma_lo, s1 label
13113 s_sext_i32_i16 tma_hi, s1 label
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt99 # VI: s_sext_i32_i16 s1, s2 ; encoding: [0x02,0x17,0x81,0xbe]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dsop1_vi.txt108 # VI: s_sext_i32_i16 s1, s2 ; encoding: [0x02,0x17,0x81,0xbe]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSOPInstructions.td190 def S_SEXT_I32_I16 : SOP1_32 <"s_sext_i32_i16",
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUAsmGFX7.rst411 s_sext_i32_i16 dst, src0

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