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Searched refs:saddw (Results 1 – 25 of 42) sorted by relevance

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/external/libavc/common/armv8/
Dih264_weighted_pred_av8.s154 saddw v4.8h, v4.8h , v3.8b //adding offset for rows 1,2
155 saddw v6.8h, v6.8h , v3.8b //adding offset for rows 3,4
188 saddw v4.8h, v4.8h , v3.8b //adding offset for row 1
190 saddw v6.8h, v6.8h , v3.8b //adding offset for row 2
192 saddw v8.8h, v8.8h , v3.8b //adding offset for row 3
194 saddw v10.8h, v10.8h , v3.8b //adding offset for row 4
234 saddw v12.8h, v12.8h , v3.8b //adding offset for row 1L
236 saddw v14.8h, v14.8h , v3.8b //adding offset for row 1H
239 saddw v16.8h, v16.8h , v3.8b //adding offset for row 2L
242 saddw v18.8h, v18.8h , v3.8b //adding offset for row 2H
[all …]
Dih264_weighted_bi_pred_av8.s185 saddw v4.8h, v4.8h , v3.8b //adding offset for rows 1,2
186 saddw v8.8h, v8.8h , v3.8b //adding offset for rows 3,4
225 saddw v4.8h, v4.8h , v3.8b //adding offset for row 1
227 saddw v8.8h, v8.8h , v3.8b //adding offset for row 2
228 saddw v12.8h, v12.8h , v3.8b //adding offset for row 3
230 saddw v16.8h, v16.8h , v3.8b //adding offset for row 4
287 saddw v20.8h, v20.8h , v3.8b //adding offset for row 1L
289 saddw v4.8h, v4.8h , v3.8b //adding offset for row 1H
291 saddw v24.8h, v24.8h , v3.8b //adding offset for row 2L
293 saddw v8.8h, v8.8h , v3.8b //adding offset for row 2H
[all …]
Dih264_iquant_itrans_recon_av8.s677 saddw v24.4s, v24.4s, v9.4h
680 saddw v26.4s, v26.4s, v13.4h
690 saddw v24.4s, v24.4s, v16.4h
693 saddw v26.4s, v26.4s, v19.4h
/external/llvm/test/MC/AArch64/
Dneon-3vdiff.s301 saddw v0.8h, v1.8h, v2.8b
302 saddw v0.4s, v1.4s, v2.4h
303 saddw v0.2d, v1.2d, v2.2s
Dneon-diagnostics.s2647 saddw v0.8h, v1.8h, v2.8h
2648 saddw v0.4s, v1.4s, v2.4s
2649 saddw v0.2d, v1.2d, v2.2d
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-3vdiff.s301 saddw v0.8h, v1.8h, v2.8b
302 saddw v0.4s, v1.4s, v2.4h
303 saddw v0.2d, v1.2d, v2.2s
Dneon-diagnostics.s2602 saddw v0.8h, v1.8h, v2.8h
2603 saddw v0.4s, v1.4s, v2.4s
2604 saddw v0.2d, v1.2d, v2.2d
/external/capstone/suite/MC/AArch64/
Dneon-3vdiff.s.cs102 0x20,0x10,0x22,0x0e = saddw v0.8h, v1.8h, v2.8b
103 0x20,0x10,0x62,0x0e = saddw v0.4s, v1.4s, v2.4h
104 0x20,0x10,0xa2,0x0e = saddw v0.2d, v1.2d, v2.2s
/external/libhevc/common/arm64/
Dihevc_deblk_luma_horz.s505 saddw v4.8h, v6.8h , v7.8b
530 saddw v14.8h, v14.8h , v7.8b
537 saddw v16.8h, v16.8h , v14.8b
569 saddw v16.8h, v16.8h , v14.8b
Dihevc_deblk_luma_vert.s530 saddw v16.8h, v16.8h , v20.8b
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/AArch64/
Dfree-widening-casts.ll370 ; CODE: saddw v0.8h, v1.8h, v0.8b
380 ; CODE: saddw v0.4s, v1.4s, v0.4h
390 ; CODE: saddw v0.2d, v1.2d, v0.2s
401 ; CODE-NEXT: saddw v0.8h, v1.8h, v0.8b
412 ; CODE-NEXT: saddw v0.4s, v1.4s, v0.4h
423 ; CODE-NEXT: saddw v0.2d, v1.2d, v0.2s
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vadd.ll360 ;CHECK: saddw.8h
370 ;CHECK: saddw.4s
380 ;CHECK: saddw.2d
390 ;CHECK: saddw.8h
403 ;CHECK: saddw.4s
416 ;CHECK: saddw.2d
Darm64-neon-3vdiff.ll187 ; CHECK: saddw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
196 ; CHECK: saddw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
205 ; CHECK: saddw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
/external/llvm/test/CodeGen/AArch64/
Darm64-vadd.ll360 ;CHECK: saddw.8h
370 ;CHECK: saddw.4s
380 ;CHECK: saddw.2d
Darm64-neon-3vdiff.ll187 ; CHECK: saddw {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8b
196 ; CHECK: saddw {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4h
205 ; CHECK: saddw {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2s
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1370 # CHECK: saddw v0.8h, v1.8h, v2.8b
1371 # CHECK: saddw v0.4s, v1.4s, v2.4h
1372 # CHECK: saddw v0.2d, v1.2d, v2.2s
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1370 # CHECK: saddw v0.8h, v1.8h, v2.8b
1371 # CHECK: saddw v0.4s, v1.4s, v2.4h
1372 # CHECK: saddw v0.2d, v1.2d, v2.2s
/external/v8/src/arm64/
Dmacro-assembler-arm64.h436 V(saddw, Saddw) \
Dsimulator-arm64.h1674 LogicVRegister saddw(VectorFormat vform, LogicVRegister dst,
Dassembler-arm64.h2073 void saddw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1163 0x~~~~~~~~~~~~~~~~ 0eb21178 saddw v24.2d, v11.2d, v18.2s
1164 0x~~~~~~~~~~~~~~~~ 0e66118d saddw v13.4s, v12.4s, v6.4h
1165 0x~~~~~~~~~~~~~~~~ 0e271273 saddw v19.8h, v19.8h, v7.8b
Dlog-disasm1163 0x~~~~~~~~~~~~~~~~ 0eb21178 saddw v24.2d, v11.2d, v18.2s
1164 0x~~~~~~~~~~~~~~~~ 0e66118d saddw v13.4s, v12.4s, v6.4h
1165 0x~~~~~~~~~~~~~~~~ 0e271273 saddw v19.8h, v19.8h, v7.8b
Dlog-cpufeatures-custom1162 0x~~~~~~~~~~~~~~~~ 0eb21178 saddw v24.2d, v11.2d, v18.2s ### {NEON} ###
1163 0x~~~~~~~~~~~~~~~~ 0e66118d saddw v13.4s, v12.4s, v6.4h ### {NEON} ###
1164 0x~~~~~~~~~~~~~~~~ 0e271273 saddw v19.8h, v19.8h, v7.8b ### {NEON} ###
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1396 __ saddw(v24.V2D(), v11.V2D(), v18.V2S()); in GenerateTestSequenceNEON() local
1397 __ saddw(v13.V4S(), v12.V4S(), v6.V4H()); in GenerateTestSequenceNEON() local
1398 __ saddw(v19.V8H(), v19.V8H(), v7.V8B()); in GenerateTestSequenceNEON() local
/external/vixl/src/aarch64/
Dsimulator-aarch64.h2422 LogicVRegister saddw(VectorFormat vform,

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