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Searched refs:saddw2 (Results 1 – 25 of 34) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dneon-3vdiff.s309 saddw2 v0.8h, v1.8h, v2.16b
310 saddw2 v0.4s, v1.4s, v2.8h
311 saddw2 v0.2d, v1.2d, v2.4s
Dneon-diagnostics.s2661 saddw2 v0.8h, v1.8h, v2.16h
2662 saddw2 v0.4s, v1.4s, v2.8s
2663 saddw2 v0.2d, v1.2d, v2.4d
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-3vdiff.s309 saddw2 v0.8h, v1.8h, v2.16b
310 saddw2 v0.4s, v1.4s, v2.8h
311 saddw2 v0.2d, v1.2d, v2.4s
Dneon-diagnostics.s2616 saddw2 v0.8h, v1.8h, v2.16h
2617 saddw2 v0.4s, v1.4s, v2.8s
2618 saddw2 v0.2d, v1.2d, v2.4d
/external/capstone/suite/MC/AArch64/
Dneon-3vdiff.s.cs105 0x20,0x10,0x22,0x4e = saddw2 v0.8h, v1.8h, v2.16b
106 0x20,0x10,0x62,0x4e = saddw2 v0.4s, v1.4s, v2.8h
107 0x20,0x10,0xa2,0x4e = saddw2 v0.2d, v1.2d, v2.4s
/external/libavc/common/armv8/
Dih264_iquant_itrans_recon_av8.s678 saddw2 v25.4s, v25.4s, v9.8h
681 saddw2 v27.4s, v27.4s, v13.8h
691 saddw2 v25.4s, v25.4s, v16.8h
694 saddw2 v27.4s, v27.4s, v19.8h
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/CostModel/AArch64/
Dfree-widening-casts.ll400 ; CODE: saddw2 v2.8h, v2.8h, v0.16b
411 ; CODE: saddw2 v2.4s, v2.4s, v0.8h
422 ; CODE: saddw2 v2.2d, v2.2d, v0.4s
/external/llvm/test/CodeGen/AArch64/
Darm64-vadd.ll390 ;CHECK: saddw2.8h
403 ;CHECK: saddw2.4s
416 ;CHECK: saddw2.2d
Darm64-neon-3vdiff.ll241 ; CHECK: saddw2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
251 ; CHECK: saddw2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
261 ; CHECK: saddw2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1377 # CHECK: saddw2 v0.8h, v1.8h, v2.16b
1378 # CHECK: saddw2 v0.4s, v1.4s, v2.8h
1379 # CHECK: saddw2 v0.2d, v1.2d, v2.4s
/external/llvm/test/MC/Disassembler/AArch64/
Dneon-instructions.txt1377 # CHECK: saddw2 v0.8h, v1.8h, v2.16b
1378 # CHECK: saddw2 v0.4s, v1.4s, v2.8h
1379 # CHECK: saddw2 v0.2d, v1.2d, v2.4s
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-neon-3vdiff.ll241 ; CHECK: saddw2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.16b
251 ; CHECK: saddw2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.8h
261 ; CHECK: saddw2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.4s
/external/v8/src/arm64/
Dmacro-assembler-arm64.h435 V(saddw2, Saddw2) \
Dsimulator-arm64.h1676 LogicVRegister saddw2(VectorFormat vform, LogicVRegister dst,
Dassembler-arm64.h2076 void saddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
/external/vixl/test/test-trace-reference/
Dlog-disasm-colour1166 0x~~~~~~~~~~~~~~~~ 4eba113b saddw2 v27.2d, v9.2d, v26.4s
1167 0x~~~~~~~~~~~~~~~~ 4e7512f3 saddw2 v19.4s, v23.4s, v21.8h
1168 0x~~~~~~~~~~~~~~~~ 4e3e132f saddw2 v15.8h, v25.8h, v30.16b
Dlog-disasm1166 0x~~~~~~~~~~~~~~~~ 4eba113b saddw2 v27.2d, v9.2d, v26.4s
1167 0x~~~~~~~~~~~~~~~~ 4e7512f3 saddw2 v19.4s, v23.4s, v21.8h
1168 0x~~~~~~~~~~~~~~~~ 4e3e132f saddw2 v15.8h, v25.8h, v30.16b
Dlog-cpufeatures-custom1165 0x~~~~~~~~~~~~~~~~ 4eba113b saddw2 v27.2d, v9.2d, v26.4s ### {NEON} ###
1166 0x~~~~~~~~~~~~~~~~ 4e7512f3 saddw2 v19.4s, v23.4s, v21.8h ### {NEON} ###
1167 0x~~~~~~~~~~~~~~~~ 4e3e132f saddw2 v15.8h, v25.8h, v30.16b ### {NEON} ###
Dlog-cpufeatures1165 0x~~~~~~~~~~~~~~~~ 4eba113b saddw2 v27.2d, v9.2d, v26.4s // Needs: NEON
1166 0x~~~~~~~~~~~~~~~~ 4e7512f3 saddw2 v19.4s, v23.4s, v21.8h // Needs: NEON
1167 0x~~~~~~~~~~~~~~~~ 4e3e132f saddw2 v15.8h, v25.8h, v30.16b // Needs: NEON
Dlog-cpufeatures-colour1165 0x~~~~~~~~~~~~~~~~ 4eba113b saddw2 v27.2d, v9.2d, v26.4s NEON
1166 0x~~~~~~~~~~~~~~~~ 4e7512f3 saddw2 v19.4s, v23.4s, v21.8h NEON
1167 0x~~~~~~~~~~~~~~~~ 4e3e132f saddw2 v15.8h, v25.8h, v30.16b NEON
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc1399 __ saddw2(v27.V2D(), v9.V2D(), v26.V4S()); in GenerateTestSequenceNEON() local
1400 __ saddw2(v19.V4S(), v23.V4S(), v21.V8H()); in GenerateTestSequenceNEON() local
1401 __ saddw2(v15.V8H(), v25.V8H(), v30.V16B()); in GenerateTestSequenceNEON() local
Dtest-cpu-features-aarch64.cc1595 TEST_NEON(saddw2_0, saddw2(v0.V8H(), v1.V8H(), v2.V16B()))
1596 TEST_NEON(saddw2_1, saddw2(v0.V4S(), v1.V4S(), v2.V8H()))
1597 TEST_NEON(saddw2_2, saddw2(v0.V2D(), v1.V2D(), v2.V4S()))
/external/vixl/src/aarch64/
Dsimulator-aarch64.h2426 LogicVRegister saddw2(VectorFormat vform,
Dassembler-aarch64.h3069 void saddw2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
Dmacro-assembler-aarch64.h2585 V(saddw2, Saddw2) \

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