| /external/u-boot/drivers/clk/ |
| D | clk-hsdk-cgu.c | 369 static ulong pll_get(struct clk *sclk) in pll_get() argument
374 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); in pll_get()
401 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate) in hsdk_pll_round_rate() argument
405 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); in hsdk_pll_round_rate()
477 static ulong pll_set(struct clk *sclk, ulong rate) in pll_set() argument
481 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); in pll_set()
484 best_rate = hsdk_pll_round_rate(sclk, rate); in pll_set()
498 static int idiv_off(struct clk *sclk) in idiv_off() argument
500 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev); in idiv_off()
507 static ulong idiv_get(struct clk *sclk) in idiv_get() argument
[all …]
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| /external/u-boot/arch/arm/mach-exynos/ |
| D | clock.c | 367 unsigned long sclk = 0; in exynos5_get_periph_rate() local
437 sclk = exynos5_get_pll_clk(MPLL); in exynos5_get_periph_rate()
440 sclk = exynos5_get_pll_clk(EPLL); in exynos5_get_periph_rate()
443 sclk = exynos5_get_pll_clk(VPLL); in exynos5_get_periph_rate()
460 return (sclk / (div + 1)) / (sub_div + 1); in exynos5_get_periph_rate()
466 unsigned long sclk = 0; in exynos542x_get_periph_rate() local
528 sclk = exynos542x_get_pll_clk(MPLL); in exynos542x_get_periph_rate()
531 sclk = exynos542x_get_pll_clk(SPLL); in exynos542x_get_periph_rate()
534 sclk = exynos542x_get_pll_clk(EPLL); in exynos542x_get_periph_rate()
537 sclk = exynos542x_get_pll_clk(RPLL); in exynos542x_get_periph_rate()
[all …]
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| /external/u-boot/board/freescale/common/ |
| D | ngpixis.c | 142 PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2])); in pixis_dump_regs()
169 PIXIS_WRITE(sclk[0], sclk0); in pixis_sysclk_set()
170 PIXIS_WRITE(sclk[1], sclk1); in pixis_sysclk_set()
171 PIXIS_WRITE(sclk[2], sclk2); in pixis_sysclk_set()
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| D | ics307_clk.c | 134 in_8(&fpga_reg->sclk[0]), in get_board_sys_clk()
135 in_8(&fpga_reg->sclk[1]), in get_board_sys_clk()
136 in_8(&fpga_reg->sclk[2])); in get_board_sys_clk()
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| D | pixis.h | 33 u8 sclk[3]; member
96 u8 sclk[3]; member
128 u8 sclk[3]; member
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| D | qixis.c | 184 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]), in qixis_dump_regs()
185 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2])); in qixis_dump_regs()
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| D | ngpixis.h | 38 u8 sclk[3]; member
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| D | qixis.h | 46 u8 sclk[3]; /* Clock Configuration Registers,0x34 */ member
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| /external/u-boot/drivers/mmc/ |
| D | exynos_dw_mmc.c | 56 unsigned long sclk; in exynos_dwmci_get_clk() local
67 sclk = get_mmc_clk(host->dev_index); in exynos_dwmci_get_clk()
73 return sclk / clk_div / (host->div + 1); in exynos_dwmci_get_clk()
98 unsigned long freq, sclk; in exynos_dwmci_core_init() local
106 sclk = get_mmc_clk(host->dev_index); in exynos_dwmci_core_init()
107 div = DIV_ROUND_UP(sclk, freq); in exynos_dwmci_core_init()
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| D | dw_mmc.c | 327 unsigned long sclk; local
337 sclk = host->get_mmc_clk(host, freq);
339 sclk = host->bus_hz;
345 if (sclk == freq)
348 div = DIV_ROUND_UP(sclk, 2 * freq);
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| D | ftsdc010_mci.h | 17 uint32_t sclk; /* FTSDC010 source clock in Hz */ member
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| D | ftsdc010_mci.c | 140 if (rate >= chip->sclk / (2 * (div + 1))) in ftsdc010_clkset()
143 chip->rate = chip->sclk / (2 * (div + 1)); in ftsdc010_clkset()
418 chip->sclk = priv->minmax[1]; in ftsdc010_mmc_ofdata_to_platdata()
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| /external/u-boot/drivers/spi/ |
| D | soft_spi.c | 24 struct gpio_desc sclk; member
43 dm_gpio_set_value(&plat->sclk, bit); in soft_spi_scl()
64 dm_gpio_set_value(&plat->sclk, 0); in soft_spi_cs_activate()
223 gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, in soft_spi_probe()
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| /external/u-boot/arch/arm/dts/ |
| D | sun5i-a13.dtsi | 198 clock-output-names = "tcon-ch0-sclk";
206 clock-output-names = "tcon-ch1-sclk";
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| D | stih407-pinctrl.dtsi | 1138 sclk = <&pio33 6 ALT1 OUT>;
1150 sclk = <&pio33 6 ALT1 OUT>;
1161 sclk = <&pio32 6 ALT1 IN>;
1174 sclk = <&pio32 6 ALT1 IN>;
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| D | sun4i-a10.dtsi | 624 clock-output-names = "tcon0-ch0-sclk";
634 clock-output-names = "tcon1-ch0-sclk";
643 clock-output-names = "tcon0-ch1-sclk";
652 clock-output-names = "tcon1-ch1-sclk";
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| D | rk3328.dtsi | 858 i2s1_sclk: i2s1-sclk {
918 i2s2m0_sclk: i2s2m0-sclk {
960 i2s2m1_sclk: i2s2m1-sclk {
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| D | sun7i-a20.dtsi | 674 clock-output-names = "tcon0-ch0-sclk";
684 clock-output-names = "tcon1-ch0-sclk";
693 clock-output-names = "tcon0-ch1-sclk";
702 clock-output-names = "tcon1-ch1-sclk";
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| D | sun5i-gr8.dtsi | 458 clock-output-names = "tcon-ch0-sclk";
466 clock-output-names = "tcon-ch1-sclk";
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | nvidia,tegra20-car.txt | 138 107 sclk
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| /external/u-boot/doc/device-tree-bindings/video/ |
| D | exynos-fb.txt | 56 samsung,sclk-div: parent_clock/source_clock ratio
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| /external/libdrm/include/drm/ |
| D | amdgpu_drm.h | 919 __u32 sclk; member
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| /external/kernel-headers/original/uapi/drm/ |
| D | amdgpu_drm.h | 972 __u32 sclk; member
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| /external/libxkbcommon/xkbcommon/test/data/rules/ |
| D | evdev | 1031 compose:sclk = +compose(sclk)
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| D | evdev-xkbcommon | 1022 compose:sclk = +compose(sclk)
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