| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 370 MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg()); in runOnMachineFunction()
371 MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg()); in runOnMachineFunction()
440 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
456 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC); in runOnMachineFunction()
474 MRI.setRegAllocationHint(SDst->getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
482 MRI.setRegAllocationHint(Src2->getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
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| D | SIInstrInfo.cpp | 4979 MRI.setRegAllocationHint(UnusedCarry, 0, AMDGPU::VCC); in getAddNoCarry()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIShrinkInstructions.cpp | 284 MRI.setRegAllocationHint(Dest.getReg(), 0, Src0.getReg()); in runOnMachineFunction()
338 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
354 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC); in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | CalcSpillWeights.cpp | 158 mri.setRegAllocationHint(li.reg, 0, hint); in CalculateWeightAndHint()
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| D | RegAllocLinearScan.cpp | 1012 mri_->setRegAllocationHint(cur->reg, 0, Reg); in assignRegOrStackSlotAtInterval()
1128 mri_->setRegAllocationHint(NextReloadLI->reg, 0, physReg); in assignRegOrStackSlotAtInterval()
1363 mri_->setRegAllocationHint(i->reg, 0, 0); in assignRegOrStackSlotAtInterval()
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| D | LiveInterval.cpp | 558 MRI->setRegAllocationHint(reg, Hint.first, Hint.second); in Copy()
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| D | LiveIntervalAnalysis.cpp | 1272 mri_->setRegAllocationHint(NewVReg, Hint.first, Hint.second); in rewriteInstructionForSpills()
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| /external/llvm/lib/CodeGen/ |
| D | CalcSpillWeights.cpp | 210 mri.setRegAllocationHint(li.reg, 0, hint); in calculateSpillWeightAndHint()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 670 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() function
679 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); in setSimpleHint()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 251 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 755 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() function
772 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); in setSimpleHint()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 325 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
327 MRI->setRegAllocationHint(NewReg, in updateRegAllocHint()
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| D | ARMLoadStoreOptimizer.cpp | 2270 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2271 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseRegisterInfo.cpp | 353 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in updateRegAllocHint()
355 MRI->setRegAllocationHint(NewReg, in updateRegAllocHint()
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| D | ARMLoadStoreOptimizer.cpp | 2316 MRI->setRegAllocationHint(FirstReg, ARMRI::RegPairEven, SecondReg); in RescheduleOps()
2317 MRI->setRegAllocationHint(SecondReg, ARMRI::RegPairOdd, FirstReg); in RescheduleOps()
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 1713 MRI->setRegAllocationHint(EvenReg, ARMRI::RegPairEven, OddReg); in RescheduleOps()
1714 MRI->setRegAllocationHint(OddReg, ARMRI::RegPairOdd, EvenReg); in RescheduleOps()
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| D | ARMBaseRegisterInfo.cpp | 583 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); in UpdateRegAllocHint()
|